Fishing – trapping – and vermin destroying
Patent
1994-05-18
1995-10-24
Fourson, George
Fishing, trapping, and vermin destroying
437 47, 437 60, 437919, 437 29, 437915, H01L 2170, H01L 2700
Patent
active
054609941
ABSTRACT:
A semiconductor device, e.g., a DRAM, having vertical conduction transistors and cylindrical cell gates, which includes a plurality of spaced-apart trench isolation regions formed in a semiconductor substrate, a plurality of bit lines formed on the semiconductor substrate, a silicon pillar formed on each bit line, a gate insulating layer and gate line formed on each silicon pillar in surrounding relationship thereto, a planarizing layer formed in recesses in the gate lines, an insulating layer formed on the upper surfaces of the gate line and planarizing layer, a plurality of contact holes provided in vertically aligned portions of the insulating layer, the gate line, and the gate insulating layer located above respective ones of the silicon pillars, and, a storage node of a capacitor formed with the contact holes and adjacent surface portions of the insulating layer, in contact with the source region of respective ones of the silicon pillars. Each of the silicon pillars includes vertically stacked layers which serve as respective drain, channel, and source regions of a transistor.
REFERENCES:
patent: 5106775 (1992-04-01), Kaga et al.
patent: 5316962 (1994-05-01), Matsuo et al.
patent: 5372964 (1994-12-01), Groton
Donohoe Charles R.
Fourson George
Samsung Electronics Co,. Ltd.
Tsai H. Jey
Westerlund Robert A.
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