Semiconductor device having triple diffusion

Details Semiconductor device having triple diffusion Semiconductor device having triple diffusion

1995-06-07

1997-04-22

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257336, 257344, 257408, H01L 2976

Patent

active

056231547

ABSTRACT:
An isolating/insulating film is formed on the surface of a p.sup.- silicon substrate in an element isolating region. An nMOS transistor having a pair of n-type source/drain regions is formed within an element forming region isolated by the isolating oxide film. A p.sup.+ impurity diffusion region is formed on the p.sup.- silicon substrate in such a manner as to be contacted with the lower surface of the isolating oxide film in the element isolating region and to extend at a specified depth from the surface of the p.sup.- silicon substrate in the element forming region. A p-type impurity diffusion region having a p-type impurity concentration higher than that of the p.sup.- silicon substrate is formed at the side end portion of the isolating oxide film in such a manner as to be contacted with the n-type source/drain region. With this arrangement, it is possible to reduce leakage current caused by the distribution of crystal defects in a depletion layer.

REFERENCES:
patent: 4649629 (1987-03-01), Miller et al.
patent: 5359221 (1994-10-01), Miyamoto et al.
patent: 5449937 (1995-09-01), Arimura et al.
patent: 5466957 (1995-11-01), Yuki et al.
"MOS Field Effect Transistor" edited by TAkuo Sugano, et al., Nikkan Kogyo.
"Surface Effects on p-n Junctions: Characteristics of Surface Space-Charge Regions Under Non-Equilibrium Conditions", A.S. Grove et al., Solid-State Electronics Pergamon Press 1966, vol. 9.

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