Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2011-01-11
2011-01-11
Yoha, Connie C (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S185090, C365S226000, C365S233100
Reexamination Certificate
active
07869289
ABSTRACT:
A semiconductor device has a transmission control circuit comprising a signal transmission circuit, an output control circuit, a replica circuit and a detection circuit. The single transmission circuit receives a predetermined signal in synchronization with a first control signal, and transmits and outputs the signal through a signal bus in synchronization with a second control signal. The output control circuit supplies the second control signal and controls an output timing thereof. The replica circuit transmits and outputs a replica signal (having level shifted in response to the input timing of the predetermined signal) through a replica signal bus having the same transmission characteristics as the signal bus. The detection circuit detects shifting of the replica signal and supplies a feedback signal to the output control circuit whose output timing is controlled in accordance with the shifting timing of the replica signal based on the feedback signal.
REFERENCES:
patent: 7456668 (2008-11-01), Nakanishi et al.
patent: 2002/0008586 (2002-01-01), Nakamichi
patent: 2005/0286324 (2005-12-01), Arakawa
patent: 2010/0213967 (2010-08-01), Negishi
patent: 2006-012229 (2006-01-01), None
Fujishiro Keisuke
Kato Hideaki
Elpida Memory Inc.
Sughrue & Mion, PLLC
Yoha Connie C
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