Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1997-12-22
2002-12-24
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S760000
Reexamination Certificate
active
06498398
ABSTRACT:
BACKGROUND OF THE INVENTION
(i) Field of the Invention
The present invention relates to a semiconductor device and a process for production thereof. More particularly, the present invention relates to a fine wiring structure of semiconductor device and a process for production thereof.
(ii) Description of the Prior Art
As the semiconductor elements of semiconductor device become finer, the semiconductor device must have a finer multi-layered wiring structure. Currently, in semiconductor devices having such a multi-layered wiring structure, there is mainly used, as the inter-level isolation film, a silicon oxide-based isolation film of relatively small dielectric constant and stable quality so that the parasitic capacitance between upper-layer wirings and lower-layer wirings and between adjacent wirings in the same wiring layer level can be reduced.
As the semiconductor elements become finer, the wiring width and wiring-to-wiring distance of lower-layer wirings are made smaller; however, in order to avoid an increase in wiring resistance, the wirings in said wiring layer level must have a certain cross-sectional area. As a result, both the aspect ratio of a wiring (wiring height/wiring width) and the aspect ratio between wirings (wiring height/wiring-to-wiring distance) become large. This invites a significant increase in parasitic capacitance between wirings, resulting in (1) reduction in transfer speed of signal and (2) frequent occurrence of cross-talk between wiring layers (occurrence of signal noise between adjacent wirings).
Further, if the inter-level isolation film has a large step in the surface, when an upper wiring layer is formed, it is impossible to form a fine resist pattern by photolithography owing to the shortage of focus margin. Even if it is possible, the above-mentioned difference in surface level gives rise to (1) the wiring disconnection in upper-layer wirings and (2) remaining of unetched wiring material at the sites of level difference. Thus, the inter-level isolation film must have a flat surface.
In order to avoid the above-mentioned problems appearing in a fine multi-layered wiring structure, there have been proposed various techniques of using an inter-level isolation film of low dielectric constant. An example of such techniques is a technique disclosed in Japanese Patent Application Laid-Open No. 55913/1996. This technique is described below with reference to FIG.
7
and
FIG. 8
, both of which are sectional views showing the key production steps of the wiring structure used in the technique.
As shown in FIG.
7
(
a
), a thick isolation film
101
is formed on a semiconductor substrate. On the thick isolation film
101
are formed a metal layer
102
and a first dielectric layer
103
in this order. On the first dielectric layer
103
is provided a resist mask
104
. The first dielectric layer
103
is a highly reliable isolation film made of silicon oxide or the like.
Then, the first dielectric layer
103
and the metal layer
102
are subjected to reactive ion etching (RIE) by using the resist mask
104
as an etching mask. Thereafter, the remaining resist mask
104
is removed. Thus, as shown in FIG.
7
(
b
), wirings
105
of small wiring-to-wiring distance and wirings
106
of large wiring-to-wiring distance are formed on the thick isolation film
101
.
Next, as shown in FIG.
7
(
c
), a low-dielectric constant material
107
is applied so as to cover the whole surfaces of the thick isolation film
101
, the wirings
105
of small wiring-to-wiring distance, the wirings
106
of large wiring-to-wiring distance and the first dielectric layer
103
, followed by levelling of the surface of the applied low-dielectric constant material. As the low-dielectric constant material
107
, there is used, for example, a dielectric made of a polymer such as Teflon (trade mark), Parylene (trade mark) or the like.
On the whole surface of the low-dielectric constant material
107
is formed a hard oxide mask
108
as a resist layer. Then, the material
107
and the mask
108
are subjected to selectvie etching. That is, as shown in FIG.
8
(
a
), the low-dielectric constant material
107
and the hard oxide mask
108
both in the region of wirings
106
of large wiring-to-wiring distance are removed and those in the region of wirings
105
of small wiring-to-wiring distance are allowed to remain.
Next, the hard oxide mask
108
on the region of the wirings
105
of small wiring-to-wiring distance is removed. As shown in FIG.
8
(
b
), the low-dielectric constant material
107
is etched back and removed down to a level lower than the upper surface of the first dielectric layer
103
by dry etching. In that case, the first dielectric layer
103
functions as an etching stopper for the low-dielectric constant material
107
. Preferably, the low-dielectric constant material
107
is not etched down to a level lower than the top of the wirings
105
of small wiring-to-wiring distance.
Next, as shown in FIG.
8
(
b
), a second dielectric layer
109
is formed by deposition on the whole surface of the resulting material, that is, so as to cover the wirings
106
of large wiring-to-wiring distance, the first dielectric layer
103
and the etched-back low-dielectric constant material
107
, then the surface of the second dielectric layer
109
is leveled. The second dielectric layer
109
is an isolation film made of silicon oxide or the like.
As above, on the thick isolation film
101
formed on a semiconductor substrate are formed lower-layer wirings and inter-level isolation films. In that case, a highly reliable isolation film made of silicon oxide or the like is formed in the region of large wiring-to-wiring distance, and a low-dielectric constant material is filled in the region of small wiring-to-wiring distance.
In forming a multi-layered wiring structure (this is not mentioned in the above literature), it is necessary to connect the lower-layer wirings formed by the prior art, with upper-layer wirings. In that case, as shown in FIG.
8
(
c
), throughholes
110
and
110
a
are formed on a wiring
106
of large wiring-to-wiring distance and a wiring
105
of small wiring-to-wiring distance, respectively. Into the throughholes
110
and
110
a
are formed metal plugs
111
and
111
a,
respectively, and the lower-layer wirings and the upper-layer wirings are electrically connected with the metal plugs.
In the prior art as mentioned above, an isolation film of low-dielectric constant is selectively formed in the region of small wiring-to-wiring distance, of the wiring structure of semiconductor device. In this prior art, etching back of low-dielectric constant material
107
is necessary as mentioned with respect to FIG.
8
(
b
). However, in the etching back, the etching-back depth of low-dielectric constant material is very difficult to control. It is also difficult to improve the uniformity of etching-back depth in a semiconductor wafer. Therefore, it is difficult to apply the prior art to production of a semiconductor having a fine wiring structure or using a semiconductor wafer of large diameter (e.g. diameter of 12 in.).
In the prior art, a first dielectric layer
103
and a second dielectric layer
109
are formed on or above both wirings
105
of small wiring-to-wiring distance and wirings
106
of large wiring-to-wiring distance. That is, no low-dielectric constant material
107
is formed on these wirings. Therefore, throughholes can be formed on these wirings. However, if mask alignment is deviated form the predetermined position as shown in FIG.
8
(
c
) in the photolithography employed for throughhole formation, the low-dielectric constant material
107
is also etched in the region of wirings
105
of small wiring-to-wiring distance. When the low-dielectric constant material
107
is made of a polymer having a relative dielectric constant of 3 or less such as mentioned in the above-cited literature, the throughhole
110
a
formed in the region of wirings
105
of small wiring-to-wiring distance has a very disadvantageous shape. That is, the throug
Cao Phat X.
Choate Hall & Stewart
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