Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-01-05
2001-09-11
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S189050, C365S230080
Reexamination Certificate
active
06288956
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and more particularly to a semiconductor device having a function of setting a test mode.
2. Description of the Background Art
Conventionally, a semiconductor device has a test mode circuit to set a test mode which is an operation mode for test facilitation. When a prescribed test mode is set by the test mode circuit, the semiconductor device operates according to the prescribed test mode. Thus, the inner state of the semiconductor device can be tested easily.
However, the conventional test mode circuit in a semiconductor device is formed so that a prescribed test mode is set by one setting operation. It is therefore impossible to freely combine several test modes (test operations) by a test program.
When the conventional test mode circuit is used, a test mode is entered by one setting operation and therefore a false test mode may be set according to the state of an unexpected input signal.
SUMMARY OF THE INVENTION
Therefore, the present invention provides a semiconductor device capable of combining and setting a plurality of test modes.
According to one aspect of the present invention, a semiconductor device includes an internal circuit and a plurality of test mode setting circuits receiving an input signal, the plurality of test mode setting circuits each including a test mode signal generation circuit outputting a test mode signal for setting a test mode of the internal circuit according to the input signal, and a hold circuit holding a state of the test mode signal.
Preferably, the plurality of test mode setting circuits are divided into a plurality of groups, the plurality of groups further each include a reset circuit resetting a state of a corresponding hold circuit according to the input signal.
Preferably, a prescribed number of test mode setting circuits of the plurality of test mode setting circuits correspond to test modes conflicting with each other, and the prescribed number of test mode setting circuits each operate so that, when one test mode of the conflicting test modes is set, remaining at least one conflicting test mode is not set.
According to the above described semiconductor device, a plurality of test mode signals can be set serially and in an arbitrary combination. Further, test mode signals can be reset on a group basis. Furthermore, serial setting of conflicting test mode signals can be prevented. Thus, a test program is set more freely, thereby enabling more accurate testing.
The present invention also provides a semiconductor device capable of reliably implementing a desirable test mode.
According to another aspect of the present invention, a semiconductor device includes an internal circuit, a plurality of test mode setting circuits receiving an input signal, and a test mode detection circuit for generating a test mode enable signal according to the input signal, the plurality of test mode setting circuits each including a test mode signal generation circuit responsive to the test mode enable signal for outputting a test mode signal for setting a test mode of the internal circuit according to the input signal, and a hold circuit holding a state of the test mode signal.
Preferably, the plurality of test mode setting circuits are divided into a plurality of groups, and the plurality of groups further each include a reset circuit responsive to the test mode enable signal for resetting a state of a corresponding hold circuit according to the input signal.
Preferably, a prescribed number of test mode setting circuits of the plurality of test mode setting circuits correspond to test modes conflicting with each other, and the prescribed number of test mode setting circuits each operate so that, when one test mode of the conflicting test modes is set, remaining at least one conflicting test mode is not set.
According to the above described semiconductor device, the test mode detection circuit is provided to detect a test mode, and therefore a plurality of test mode signals can be set serially and in an arbitrary combination. As a result, a combination of arbitrary test modes can be implemented without setting a false test mode signal. At this time, test mode signals can be reset on a group basis. Furthermore, serial setting of conflicting test mode signals can be prevented. Thus, a desirable test can be implemented reliably.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5400290 (1995-03-01), Suma et al.
patent: 5528162 (1996-06-01), Sato
patent: 5793685 (1998-08-01), Suma
patent: 5898316 (1999-04-01), Kato et al.
Asakura Mikio
Kato Tetsuo
Konishi Yasuhiro
Miyamoto Takayuki
Tanizaki Tetsushi
Fears Terrell W.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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