Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2005-12-20
2005-12-20
Flynn, Nathan J. (Department: 2826)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S189090, C365S226000
Reexamination Certificate
active
06977850
ABSTRACT:
A memory cell array has memory cells arranged in a matrix form. The memory cell includes a floating gate and a control gate. Word lines are each coupled to the control gates of the memory cells which are arranged on a corresponding one of the rows in the memory cell array. Bit lines are each coupled to drains of the memory cells which are arranged on a corresponding one of the columns in the memory cell array. An external voltage is supplied from the exterior to an external voltage input terminal. A first voltage generating circuit lowers the external voltage to generate a voltage which is to be supplied to the word line coupled to the control gates. A second voltage generating circuit lowers the external voltage to generate a voltage which is to be supplied to the bit line coupled to the drains.
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Kabushiki Kaisha Toshiba
Mandala Jr. Victor A.
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