Semiconductor device having stress and its manufacture method

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S510000, C257SE27015

Reexamination Certificate

active

10970158

ABSTRACT:
A semiconductor device has: active regions including a p-type active region; an insulated gate electrode structure formed on each of the active regions, and having a gate insulating film and a gate electrode formed thereon; side wall spacers formed on side walls of the insulated gate electrode structures; source/drain regions having extension regions having the opposite conductivity type to that of the active region and formed on both sides of the insulated gate electrode structures and source/drain diffusion layers having the opposite conductivity type and formed in the active regions outside of the side wall spacers; first recess regions formed by digging down the n-type source/drain regions in the p-type active region from surfaces of the n-type source/drain regions; and a first nitride film having tensile stress formed covering the p-type active region and burying the first recess regions.

REFERENCES:
patent: 6352885 (2002-03-01), Wieczorek et al.
patent: 2005/0035470 (2005-02-01), Ko et al.
patent: 2005/0224867 (2005-10-01), Huang et al.
patent: 2005/0258515 (2005-11-01), Chidambarrao et al.
patent: 2003-86708 (2003-03-01), None
patent: 2004-127957 (2004-04-01), None
T. Ghani et al., A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors, 2003 IEDM Technical Digest, pp. 978-980.

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