Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2011-08-02
2011-08-02
Dinh, Son T (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S207000, C365S189110
Reexamination Certificate
active
07990793
ABSTRACT:
A semiconductor device has a DRAM cell configured from an information charge accumulating capacitor and a memory cell selecting transistor, the threshold voltage value of a MOS transistor that constitutes a sense circuit is monitored, and the monitored threshold voltage value of the MOS transistor is converted through the use of a transfer ratio that is determined based on the capacitance of the information charge accumulating capacitor and the parasitic capacitance of the bit line. The converted voltage value is level-shifted so that the pre-charge voltage of a pre-charge circuit is a pre-set voltage, a current feeding capability is added to the level-shifted voltage value, and the voltage is fed as the pre-charge voltage.
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Korean Office Action dated Sep. 29, 2010, with partial Japanese and English translation.
Dinh Son T
Elpida Memory Inc.
McGinn IP Law Group PLLC
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