Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-10-20
2001-07-03
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S664000, C438S683000
Reexamination Certificate
active
06255215
ABSTRACT:
FIELD OF THE INVENTION
The present invention is generally directed to semiconductor devices and, more particularly, to the fabrication of silicide layers using a metal layer formed by collimated deposition.
BACKGROUND OF THE INVENTION
Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic regions. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, complimentary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors, etc.
Each of these semiconductor devices generally include a semiconductor substrate on which a number of transistors are formed. The particular structure of a given transistor can vary between transistor types. For example, MOS transistors generally include source and drain regions and a gate electrode which modulates current between the source and drain regions. Bipolar transistors generally include a base, a collector, and an emitter. In addition to these active regions (e.g., source regions, drain regions, gate electrodes, bases, emitters, collectors, etc.) of the transistors, both bipolar and MOS transistors often include polysilicon lines, active regions which typically run over regions of the substrate, such as field oxide regions, and interconnect various portions of the region.
The various active regions on a semiconductor device are typically interconnected by metal lines. In most cases, a silicide or silicidation layer is formed over some or all of the active regions in order to facilitate contact between the active regions and subsequent metal lines. The silicide layers also serve to reduce the sheet resistance of the active regions. Silicide layers are typically formed by depositing, usually by physical or chemical vapor deposition, a layer of metal, such as tungsten, platinum, cobalt or titanium, over a substrate and annealing the substrate, typically in a two-step process. During the annealing process, the deposited metal reacts with underlying silicon and forms a metal silicide layer.
The resistivity and diffusion rate of the silicide layers of a semiconductor device substantially impacts device performance. Operating speeds of a semiconductor, in particular, decrease as the resistivity of a silicide layer increases. Semiconductor manufacturers consequently continually seek to reduce the resistivity and grain morphology of silicide layers used in semiconductors and find processes which reduce silicide resistance extremely beneficial.
SUMMARY OF THE INVENTION
The present invention provides a process for forming a silicide layer using a collimated metal layer. By using a collimated metal layer, the resistance of the resultant metal silicide layer can be reduced as compared to metal silicide layers formed using conventional techniques. A semiconductor fabrication process, in accordance with one embodiment of the invention, includes depositing a collimated metal layer over a silicon active region and reacting the collimated metal layer with the silicon active region to form a metal silicide on the silicon active region.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.
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“Silicon Processing for the VLSI Era vol. 2—Process Integration” S. Wolf, Lattice Press, Sunset Beach California, 1990, pp. 144-152.
Brennan William S.
Hause Fred
May Charles E.
Advanced Micro Services
Elms Richard
Smith Brad
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