Active solid-state devices (e.g. – transistors – solid-state diode – Including semiconductor material other than silicon or... – Containing germanium – ge
Reexamination Certificate
2002-09-12
2004-01-13
Nguyen, Cuong (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Including semiconductor material other than silicon or...
Containing germanium, ge
C257S350000, C257S408000, C257S412000
Reexamination Certificate
active
06677660
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-235073, filed Aug. 12, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and a method of manufacturing the same and more particularly to a semiconductor device having a silicide film and a method of manufacturing the same.
2. Description of the Related Art
As the performance of a MOS transistor is more enhanced, it becomes more popular to form the gate electrode in a silicide form in order to reduce the parasitic resistive component thereof. For an integrated circuit such as an SRAM which requires extremely high integration density, a transistor structure in which the gates of an NMOS transistor and a PMOS transistor are used as one Si gate pattern and a junction portion between an N+ diffusion layer and P+ diffusion layer in the Si gate pattern is short-circuited by use of a silicide film is formed.
In a case where the N+ diffusion layer and P+ diffusion layer are thus formed in the same Si gate pattern, normally, the Si gate pattern is formed with a resist mask and N-type and P-type impurities are selectively ion-implanted. At this time, the N+ diffusion layer and P+ diffusion layer may be superposed depending on the alignment position of the resist mask and an impurity mixture region in which N-type and P-type impurities exist in a mixed form may be formed in the Si gate pattern in some cases. The thickness of a natural oxide film formed on the surface of the impurity mixture region is different from the thickness of a natural oxide film formed on the surface of the N+ diffusion layer and the thickness of a natural oxide film formed on the surface of the P+ diffusion layer.
Further, it is known that the natural oxide film formed on the surface of the P+ diffusion layer is more difficult to remove than the natural oxide film formed on the surface of the N+ diffusion layer. More specifically, since the concentration of holes in the natural oxide film or oxide film formed on the surface of the P+ diffusion layer becomes higher, it is difficult to completely remove the oxide film.
Reference document: Sato et al. “Study of HF-Treated Heavily-Doped Si Surface Using Contact Angle Measurements” Jpn. J. Appl. Phys. Vol. 33 (1994), pp 6508 to 6513.
When a silicide film is formed on the surface of the Si gate pattern, a step of removing the natural oxide film from the surface of the Si gate pattern is provided as the preprocessing step. However, if the thickness of the natural oxide film formed on the surface of the Si gate pattern varies and the difficulty in removing the natural oxide film varies, the natural oxide film cannot be completely removed in the preprocessing step and may be partly left behind on the surface of the Si gate pattern in some cases. The thus remaining region of the natural oxide film will obstruct the silicidation reaction between Si and metal. As a result, the resistance may increase in the remaining region of the natural oxide film in the Si gate pattern and an “open” defect may occur. Next, an example of the problem is explained.
FIGS. 33A
to
33
E are cross sectional views showing a manufacturing method of the conventional semiconductor device in the order of the manufacturing steps and particularly showing a case wherein an impurity mixture region is formed in the Si gate pattern.
First, as shown in
FIG. 33A
, a P+ diffusion layer
104
, N+ diffusion layer
105
and N+/P+ mixed layer
107
are formed in an Si gate pattern
101
. Further, a natural oxide film
110
is formed on the surface of the Si gate pattern
101
and, particularly, the film thickness t
107
of the natural oxide film formed on the surface of the impurity mixture region
107
is different from the film thickness t
104
of the natural oxide film formed on the surface of the P+ diffusion layer
104
and the film thickness t
105
of the natural oxide film formed on the surface of the N+ diffusion layer. Specifically, the film thickness t
107
is larger than the film thickness t
104
and the film thickness t
105
.
Next, as shown in
FIG. 33B
, the natural oxide film
110
is etched by a wet etching process using hydrofluoric acid or the like. At this time, it is assumed that the natural oxide film
110
is partly left behind on the surface of the impurity mixture region
107
.
Then, as shown in
FIG. 33C
, a metal film
111
is formed on the Si gate pattern
101
with the natural oxide film
110
partly left behind thereon.
After this, as shown in
FIG. 33D
, the heat treatment is performed to cause a reaction between the Si gate pattern
101
and the metal film
111
so as to form a silicide film
109
. At this time, since the reaction is difficult to occur on the natural oxide film
110
, the silicide film
109
is not practically formed on the natural oxide film
110
.
Next, as shown in
FIG. 33E
, a non-reacted portion of the metal film
111
is removed. Thus, the Si gate pattern
101
whose surface is formed in a silicide form can be obtained.
However, since the silicide film
109
is not practically formed on the impurity mixture region
107
, the silicide film
109
is divided on a boundary portion
106
between the P+ diffusion layer
104
and the N+ diffusion layer
105
. As a result, a junction portion between the P+ diffusion layer
104
and the N+ diffusion layer
105
cannot be short-circuited by use of the silicide film
109
. For example, this may be a cause of the “open” defect.
FIGS. 34A
to
34
E are cross sectional views showing another manufacturing method of the conventional semiconductor device in the order of the manufacturing steps and particularly showing a case wherein a natural oxide film is left behind on the surface of a P+ diffusion layer.
First, as shown in
FIG. 34A
, a P+ diffusion layer
104
and N+ diffusion layer
105
are formed in an Si gate pattern
101
and a natural oxide film
110
is formed on the surface of the Si gate pattern
101
.
Next, as shown in
FIG. 34B
, the natural oxide film
110
is etched by a wet etching process using hydrofluoric acid or the like. At this time, it is assumed that the natural oxide film
110
is partly left behind on the surface of the P+ diffusion layer
104
.
Then, as shown in
FIG. 34C
, a metal film
111
is formed on the Si gate pattern
101
with the natural oxide film
110
partly left behind thereon.
After this, as shown in
FIG. 34D
, the heat treatment is performed to cause a reaction between the Si gate pattern
101
and the metal film
111
so as to form a silicide film
109
. At this time, as explained with reference to
FIG. 33D
, the silicide film
109
is not practically formed on the natural oxide film
110
.
Next, as shown in
FIG. 34E
, a non-reacted portion of the metal film
111
is removed. Thus, the Si gate pattern
101
whose surface is formed in a silicide form can be obtained.
However, since the silicide film
109
is not practically formed on the natural oxide film
110
, the silicide film
109
is divided on the P+ diffusion layer
104
. As a result, the resistance will increase on a region of the P+ diffusion layer
104
on which the natural oxide film
110
is left behind.
The problems caused by leaving behind the natural oxide film
10
on the Si gate pattern
101
can be solved by increasing an etching amount of the natural oxide film
110
in the steps shown in
FIGS. 33B and 34B
, for example. However, if an etching amount of the natural oxide film
110
is increased, excessive etching will occur in a portion of the integrated circuit, for example, in the element isolation region. Next, a typical example of a problem caused by the excessive etching is explained below.
FIGS. 35
to
39
are cross sectional views showing a manufacturing method of the conventional semicond
Matsuda Satoshi
Ohuchi Kazuya
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