Semiconductor device having shallow trench isolation...

Details Semiconductor device having shallow trench isolation... Semiconductor device having shallow trench isolation...

2006-05-12

2009-11-24

Smith, Bradley K (Department: 2894)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S510000, C257S524000, C257SE21546, C257SE21549, C257SE21564

Reexamination Certificate

active

07622778

ABSTRACT:
In one embodiment, a semiconductor device has an active region defined by an isolation layer formed inside an STI trench that includes an upper trench and a lower trench having a substantially curved cross-sectional profile under the upper trench so that the lower trench is in communication with the upper trench. Since the upper trench has a sidewall tapered with a positive slope, a good gap filling property can be obtained when filling the upper trench with an insulating layer. By forming a void in the lower trench, a dielectric constant at the bottom of the isolation layer is lower than a dielectric constant at an oxide layer, thereby improving the isolation property. The isolation layer includes a first insulating layer formed inside only the upper trench and covering an inner wall of the upper trench in the form of a spacer.

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English language abstract of Korean Publication No. 1999-0073644, Jan. 29, 2007.
English language abstract of Korean Publication No. 2001-0001202, May 1, 2001.
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