Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2005-05-24
2005-05-24
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S189090, C365S205000, C365S211000
Reexamination Certificate
active
06898104
ABSTRACT:
A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense amplifier. The bit line is connected to the memory cells and applied with a voltage read from each memory cell of the memory cell array. The /bit line is supplied with a reference voltage. The reference voltage generating circuit generates the reference voltage that has temperature dependence for compensating a change in the voltage, read to the bit line, due to temperature. The reference voltage generating circuit controls the reference voltage such that the reference voltage assumes a midpoint of trails of a signal value distribution indicative of “0” data and a signal value distribution indicative of “1” data. The sense amplifier compares the voltage, read to the bit line, with the reference voltage supplied to the /bit line, and amplifies the difference therebetween.
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Ryu Ogiwara, et al., A 0.5-μm. 3-V, 1T1C, FRAM with a Variable Reference Bit-Line Voltage Scheme using a Fatigue-Free Reference Capacitor, IEEE Journal of Solid-State Circuits, vol. 35, No. 4, Apr. 2000, pp. 545-551.
Jacob Michael
Ogiwara Ryu
Takashima Daisaburo
Ho Hoai
Infineon - Technologies AG
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