Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1997-02-27
2001-02-27
Moise, Emmanuel L. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S719000, C714S720000, C365S201000, C365S230030
Reexamination Certificate
active
06195771
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device having a semiconductor memory circuit whose operation is tested in combination with an external test means, a layout of the semiconductor device and a method of testing the semiconductor memory circuit.
2. Description of the Related Art
A built-in self test (hereinafter called “BIST”) has been known as a test on the operation of a semiconductor device. As references about the BIST, there have been disclosed the following ones: (1) “A 45 ns 64 Mb DRAM with a Merged Match-line Test Architecture”, S. Mori et al, IEEE, Dige. of Tech. Papers, P. 110-111, 1991, (2) “Design and Test on Computer”, by H. Fujiwara, issued by Engineering book publisher, P204-208, and (3) “55 ns 16 Mb DRAM provided with a Self-Test Function”, Koike et al, Singaku Giho SDM69-39, P79-85, 1999, etc.
Further, “A zero-Overhead Self-Timed 160 ns 546 CMOS Divider” Williams, T. E. et al, ISSCC, Dig. of Tech. Papers, P98-99, 1991 has been disclosed as a reference about a method of controlling a FIFO (First-In First-Out) circuit related to a test.
In the prior art typified by the above-described disclosures, however, since the amount of transfer of data between a semiconductor device and an external test means increases with a great increase in the capacity of a memory portion of a semiconductor memory circuit, the time required to test the semiconductor memory circuit becomes longer. An increase in the rate of compression of data is also considered as a method of reducing the amount of transfer of the data therebetween. It is however understood from the result of a test based on compressed data that only the test for making a decision as to whether the compressed data is good or bad for each unit of the compressed data, can be realized. It is thus difficult to specify positions where defective data are produced. This will exert an influence on the relief of redundancy of the semiconductor memory circuit having large capacity.
Namely, the relief of its redundancy is intended for the improvement in yield by the replacement of a defective memory cell with a spare memory cell for its relief. However, the non-pinpointing or determination of the position of the defective memory cell will make it difficult to carry out the redundancy relief or will cause needless usage of a memory cell used for the relief of its redundancy because the redundancy relief is performed for each large-scale unit.
SUMMARY OF THE INVENTION
Typical ones of various inventions, which have been made by the inventors of the present application to solve the problem typified above, are shown below. The inventions other than the inventions to be described below will be understood from a detailed description to be explained later.
Namely, there is provided a semiconductor device having a semiconductor memory circuit whose operation is tested in combination with an external test means, which comprises:
a test pattern generator for generating a test pattern indicative of the type of test and an expected value estimated to be obtained by the test pattern in response to a command issued from the test means;
the semiconductor memory circuit having a plurality of memory cells disposed in the form of a matrix with rows and columns, for respectively storing data therein, and being activated based on the test pattern so as to output the data stored in the respective memory cells column by column;
a decision unit for comparing each outputted data with the expected value and outputting the result of comparison therefrom; and
a translation unit for converting the result of comparison into address data and outputting it to the external test means.
According to such a construction, since a defective one of the memory cells is specified, it can be efficiently replaced by a spare memory cell in a redundancy relieving process corresponding to a process subsequent to the execution of this specifying test. Namely, since only the defective memory cell need can be replaced by the spare memory cell during the redundancy relieving process, unnecessary waste of the spare memory cell can be eliminated and the time necessary for its replacement can be greatly shortened.
A lot of time is normally required upon the redundancy relieving process. Therefore, since the shortening of the time by such a construction contributes to a reduction in cost, the shortening of a period up to the supply of products, etc., a very great effect can be expected in a semiconductor field. Further, since the test means can be realized by such a simple configuration where only address data indicative of defective portions will be stored, the test means is available at low cost.
REFERENCES:
patent: 4559626 (1985-12-01), Brown
patent: 5706234 (1998-01-01), Pilch, Jr. et al.
patent: 8-161899 (1996-06-01), None
patent: 9-197009 (1997-07-01), None
ISSCC91/Session 5/Microprocessors/Paper TA 5.5.
ISSCC91/Session 6/High-density DRAM/Paper TA 6.4.
A 55ns 16Mb DRAM with Built-in-Self-Test Function Using Micro-Program ROM (pp. 79-85).
Design and Test of Computer (pp. 204-209).
Tanabe Tetsuya
Tanoi Satoru
Tokunaga Yasuhiro
Moise Emmanuel L.
Oki Electric Industry Co., Ltd
Rabin & Champagne, P.C.
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