Semiconductor device having semiconductor chip with backside ele

Details Semiconductor device having semiconductor chip with backside ele Semiconductor device having semiconductor chip with backside ele

1994-09-22

1996-03-05

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

257693, 257698, 257784, H01L 23053, H01L 2312

Patent

active

054970318

ABSTRACT:
A semiconductor chip is mounted on a chip-mounting section. A conduction path forming section having a plurality of conduction paths formed therein is placed around the chip-mounting section. A heat sinking board is bonded to the backsides of the chip-mounting section and the conduction path forming section. In the conduction path forming section, a second insulating layer is formed with notches, whereby the exposed area of conduction paths that are wire-bonded to the chip-mounting section is increased.

REFERENCES:
patent: 4513355 (1985-04-01), Schroeder et al.
patent: 4972253 (1990-11-01), Palino et al.
patent: 5008734 (1991-04-01), Dutta et al.
patent: 5041899 (1991-08-01), Oku et al.
patent: 5043794 (1991-08-01), Tai et al.
patent: 5173767 (1992-12-01), Lange et al.
patent: 5235209 (1993-08-01), Shimizu et al.
patent: 5331511 (1994-07-01), Lee et al.
"Electrical Design Methodology of a 407 Pin Multi Layer Ceramic Package", 39th IEEE/ECC, May 22-24, 1989, Houston, Texas, pp. 392-397.
"GaAs Multichip Module for a Parallel Processing System", 40th IEEE/ECTC, 1990, Las Vegas, Nevada, pp. 580-585.
Cicone `Silicon Integrated High Performance Package` IBM, vol. 27 No. 7B Dec. 1984 p. 4226.

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