Semiconductor device having self-aligned contact and method...

Details Semiconductor device having self-aligned contact and method... Semiconductor device having self-aligned contact and method...

2000-08-18

2004-04-06

Lee, Hsien Ming (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S640000, C438S672000, C438S675000

Reexamination Certificate

active

06716746

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and to a method of fabricating semiconductor devices. More particularly, the present invention relates to a semiconductor device having a self-aligned contact and to a method of fabricating the same.
2. Description of the Related Art
In order to fabricate semiconductor devices, several patterns of different materials, for example, a metal film pattern, a semiconductor film pattern, a dielectric film pattern, etc., are formed on a semiconductor substrate in a predetermined order. When forming these patterns on the semiconductor substrate, a mask is formed on one film pattern, i.e., an underlying film pattern, in alignment therewith, and then the overlying pattern is formed by photolithography making use of the mask in order to align the overlying film pattern with the underlying film pattern. However, the more densely integrated semiconductor devices are to become, the smaller the allowable mask alignment margin must become. That is, it is becoming more and more difficult to accurately align overlying film patterns with underlying film patterns. The mask alignment margin, therefore, presents an obstacle in increasing the integration density of semiconductor devices. In fact, if the mask alignment margin is too great, the operating characteristics of the semiconductor devices are denigrated.
One problem which occurs when underlying and overlying film patterns are mis-aligned with each other will now be described in detail with reference to
FIGS. 1 and 2
.
In the conventional semiconductor device fabrication technique, an interlayer dielectric layer
12
is formed on a semiconductor substrate
10
. Then, a contact plug
16
, which contacts a junction region
14
of a semiconductor device, for example, a source or drain region, is formed as an underlying film pattern within the interlayer dielectric layer
12
. Subsequently, a conductive layer is formed over the region where the contact plug
16
was formed. Then the conductive layer is patterned, using photolithography, to produce a conductive line
18
which represents an overlying pattern with respect to the contact plug
16
. The conductive line
18
and the contact plug
16
are often misaligned (see
FIG. 1
) due to the large margin of error inherent in the photolithography process, whereby the conductive line
18
and the contact plug
16
form a poor contact
20
.
When the contact plug
16
, which is an underlying film pattern, and the conductive line
18
, which is an overlying film pattern, are not accurately aligned, the operating characteristics of the resultant semiconductor device are adversely affected. Specifically, a reduction in the contact area between the contact plug
16
and the conductive line
18
increases the contact resistance, thereby reducing the operating speed of the semiconductor device.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of aligning underlying and overlying film patterns with each other within a small alignment margin, whereby the resultant semiconductor device is has a high integration density.
Another object of the present invention is to provide a method of fabricating semiconductor devices which is not affected by the margin of error inherent in the photolithography process.
To achieve these objects, the present invention provides a method of fabricating semiconductor devices, comprising the steps of forming a conductive region on a semiconductor substrate, forming a first interlayer dielectric layer on the entire surface of the semiconductor substrate on which the conductive region has been formed, forming a conductive line on the first interlayer dielectric layer, forming a second interlayer dielectric layer on the conductive line, removing portions of the first interlayer dielectric layer, conductive line, and second interlayer dielectric layer which are formed on the conductive region to thereby form a contact hole which exposes the conductive region, and filling the contact hole with a conductive material to connect the conductive line to the conductive region.
The conductive line may be formed by a Damascene process.
The contact hole may be formed by first forming a photosensitive film pattern on the second interlayer dielectric layer, the pattern defining an opening having a width that is greater than the critical dimension of the conductive line. Then, the conductive line is exposed by etching the second interlayer dielectric layer using the photosensitive film pattern as an etch mask. Thereafter, the contact hole is formed by etching the conductive line and the first interlayer dielectric layer. In some circumstances, the photosensitive film pattern may be removed after the conductive line is exposed.
To achieve the above-mentioned objects, the present invention also provides a method of fabricating semiconductor devices, comprising the steps of forming a conductive region on a semiconductor substrate, forming a first interlayer dielectric layer on the entire surface of the semiconductor substrate on which the conductive region has been formed, forming a conductive line on the first interlayer dielectric layer such that a portion of the conductive line has a gap therein, forming a second interlayer dielectric layer on the conductive line, forming a contact hole by removing a portion of the first interlayer dielectric layer on the conductive region, a first portion of the second interlayer dielectric layer occupying the gap in the conductive line, and a second portion of the second interlayer dielectric layer overlying the gap, and filling the contact hole with a conductive material to connect the conductive line to the conductive region.
The discontinuous conductive line may be formed by a Damascene process.
On the other hand, the contact hole may be formed by first forming a photosensitive film pattern on the second interlayer dielectric layer, the photosensitive pattern defining an opening having respective widths that are greater than the critical dimension and the width of the gap in the conductive line as taken therealong, respectively. Then, the first and second portions of the second interlayer dielectric layer, and a portion of the first interlayer dielectric layer underlying the gap in the conductive line are etched away.
Another object of the present invention is to provide a semiconductor device having a self-aligned contact, and yet also possessing a high integration density.
To achieve this object, the present invention provides a semiconductor device having a conductive region, a conductive line, and a contact plug electrically connecting the conductive line to the conductive region, wherein the conductive line is electrically connected to the conductive region via the sidewalls of the contact plug, the conductive region is electrically connected to the conductive line via the bottom of the contact plug, and the cross-sectional area of the contact plug decreases in a direction extending from the upper portion of the contact plug to the lower portion thereof.
Preferably, the lower portion of the contact plug is self-aligned with the critical dimension of the conductive line. The upper portion of the contact plug is preferably wider than the critical dimension of the conductive line.
The conductive region may be a bit line contact pad, a word line contact pad, a source region, a drain region, a gate electrode, or an interlayer wiring.
The conductive line may be a bit line, a word line, or an interlayer wiring.


REFERENCES:
patent: 5804504 (1998-09-01), Choi
patent: 5821168 (1998-10-01), Jain
patent: 5895264 (1999-04-01), Teo
patent: 6037211 (2000-03-01), Jeng et al.
patent: 6136695 (2000-10-01), Lee et al.
patent: 6228755 (2001-05-01), Kusumi et al.
patent: 1994-1273 (1994-01-01), None

Affiliated with

Also associated with

Rating

Semiconductor device having self-aligned contact and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device having self-aligned contact and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having self-aligned contact and method... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3210724