Semiconductor device having reduced interconnect-line...

Details Semiconductor device having reduced interconnect-line... Semiconductor device having reduced interconnect-line...

2001-08-29

2003-03-11

Clark, Jasmine J B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000, C257S752000, C257S758000

Reexamination Certificate

active

06531776

ABSTRACT:

This application incorporates by reference Taiwanese application Serial No. 90106123, filed on Mar. 15, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a semiconductor device and a fabrication method, and more particularly to a semiconductor device having reduced parasitic capacitance between metal lines, and to a fabrication method thereof.
2. Description of the Related Art
During semiconductor fabrication, an integrated circuit (IC) is fabricated by interconnecting a plurality of various transistors with interconnect lines successfully. According to the signal paths of a circuit design, these interconnect lines are employed for interconnecting the transistors to become a complete circuit. Such interconnect lines as metal lines doped with silicon are the main conductors used for contacts and interconnection. Generally, metal lines include conductors such as copper (Cu), aluminum (Al), or an alloy of Al and Cu, or tungsten (conductor adopted in high temperature fabrication). In addition, a single level of metal layer cannot provide interconnection for completing integrated circuits nowadays. For the requirements of integrated circuits, two, three, or even five levels of metal layers are employed, and a multiple-level interconnect technology is used to interconnect these metal layers. Further, a good insulating material, such as silicon dioxide (SiO
2
), is used for dielectric layers for separating these metal layers to avoid a short circuit.
Unfortunately, the separation of the metal lines by using insulating material leads to the formation of parasitic capacitance among the metal lines on a signal level of metal layer, resulting in a delay of speed of the integrated circuit. For two metal lines separated by a dielectric material, it is desired to reduce the capacitance between the two metal lines. Since the capacitance is proportional to the dielectric constant of the dielectric material and inversely proportional to the distance between the two metal lines, the capacitance is able to be reduced by using a dielectric material having a low dielectric constant or increasing the distance between the two metal lines. However, an increase of the distance between the two metal lines results in an increase of the size of the semiconductor device. Thus, dielectric materials having low dielectric constants are conventionally employed to reduce the parasitic capacitance between metal lines. For instance, referring to
FIG. 1
, it illustrates a cross-section view of a conventional structure of metal lines with an inter-layer dielectric. As shown in
FIG. 1
, the space between and above metal lines
104
formed on a substrate
102
is filled with silicon dioxide so that an inter-layer dielectric
106
is formed, where the dielectric constant of silicon dioxide is four.
Another technique for reducing the parasitic capacitance between the metal lines is described in L. D. Wong and B. Oreg, U.S. Pat. No. 6,057,226. The main principle of this technique is to form an air bridge between the metal lines by covering the metal lines with fluorinated amorphous carbon as the inter-layer dielectric. Since the metal lines are closely spaced, the filling by the fluorinated amorphous carbon is incomplete, resulting in the air bridge between the metal lines. In addition, the dielectric constant of the air is approximately equal to one so that the dielectric constant between the metal lines is reduced, thus reducing the parasitic capacitance.
Referring to
FIG. 2A
, it illustrates a cross-sectional view of a conventional structure of metal lines and an inter-layer dielectric. In
FIG. 2A
, metal lines
204
formed on a substrate
202
are covered with fluorinated amorphous carbon
206
so as to form air gaps
208
between metal lines
204
. An insulating layer
210
is then formed over the fluorinated amorphous carbon
206
. The disadvantage of the technique is the difficulty in controlling the flow of fluorinated amorphous carbon
206
between metal lines
204
, resulting in non-uniform sizes of air gaps
208
. In a worse case, only insignificant air gaps are formed. Besides, when metal lines
204
are spaced in a way such that a large amount of fluorinated amorphous carbon fills the space between metal lines
204
, air gaps are much more difficult to be formed. In practice, air gaps
208
are not formed so ideally as shown in FIG.
2
A.
In addition, L. D. Wong and B. Oreg provide a method to reduce the parasitic capacitance between metal lines. Referring to
FIG. 2B
, it illustrates a cross-sectional view of another structure of inter-layer dielectric and metal lines. Compared to the structure in
FIG. 2A
, the structure in
FIG. 2B
includes a hard-mask layer
212
and a liner
214
additionally.
As shown in
FIG. 2B
, hard-mask layer
212
is formed over the topsides of metal lines
204
which are formed on substrate
202
. Then, liner
214
is to cover hard-mask layer
212
, walls of metal lines
204
, and portions of the substrate
202
between metal lines
204
so as to enhance the structure. Next, fluorinated amorphous carbon
206
fills the space between and above metal lines
204
such that air gaps
208
are formed between metal lines
204
. Finally, insulating layer
210
is formed over fluorinated amorphous carbon
206
. In this way, the spacing between metal lines
204
is theoretically reduced by the addition of liner
214
, leading to an reduction of the amount of fluorinated amorphous carbon which fills the space between metal lines
204
during manufacturing process. Following that, air gaps
208
formed as shown in
FIG. 2B
are larger than that formed as shown in
FIG. 2A
, but it is still unable to control the flow of fluorinated amorphous carbon
206
. Besides, since hard-mask layer
212
has a thickness in the range of approximately 50 nm to 100 nm and liner
214
has a thickness in the range of approximately 10 nm to 100 nm, a single level of metal layer as shown in
FIG. 2B
has a larger total thickness than that as shown in
FIG. 2A
by approximately 60 nm to 100 nm, resulting in an increase in the size of the semiconductor device. Further, the addition of the hard-mask layer increases the complexity of the manufacturing process, resulting in an increase of the manufacturing cost.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a semiconductor device having reduced interconnect-line parasitic capacitance. In this invention, a dielectric with a low dielectric constant and capable of being foamed is used to fill the space between metal lines formed on a substrate. The foamed dielectric is then condensed so that a lot of small pores become large pores. In this way, the dielectric constant between the metal lines is low, reducing the parasitic capacitance between metal lines effectively. Further, a manufacturing process according to the invention is provided with no such difficulty in controlling the flow of inter-layer dielectric and the size of air gaps as in the conventional manufacturing process; and a process of forming hard-mask layer becomes unnecessary. Thus, the manufacturing process is simplified, resulting in a reduction of the manufacturing cost.
The invention achieves the above-identified object by providing a semiconductor device having reduced interconnect-line parasitic capacitance. The semiconductor includes a substrate, a barrier layer, a separation layer, and an insulating layer. The substrate has a plurality of interconnect lines formed thereon. The barrier layer is deposited on the substrate, which covers the interconnect lines and the substrate. In addition, the separation layer is deposited on the space between the interconnect lines, which is formed by filling the space between the interconnect lines with a low-k dielectric. The insulating layer is deposited above the separation layer, which covers the interconnect lines and the barrier layer.
In accordance with the object of the invention, a method of forming a semiconductor device having reduced interconnect-line parasitic capac

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