Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-07
2001-05-08
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S357000, C257S360000
Reexamination Certificate
active
06229182
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a semiconductor device comprising a semiconductor body including an integrated circuit provided with bonding pads for connecting the circuit to external supply conductors and with means for protecting the circuit against damage caused by electrostatic discharge, said means comprising at least a protection diode which is connected to a bonding pad and formed by a drain region of a field effect transistor with an insulated gate electrode, which field effect transistor includes a source region and a drain region, which are separated from each other by an intermediate channel region, said source and drain regions being formed by surface areas of a first conductivity type in a surface area of the second, opposite, conductivity type.
Such a device is disclosed, for example, in U.S. Pat. No. 5,493,142.
The use of a field effect transistor as a protection against ESD is generally known. In a much used configuration, often referred to as ggNMOST (grounded gate NMOST), the gate or gate electrode is connected, with its source region, to the bonding pad which is connected to earth or V
ss
, while the drain is connected to an I/O pad. If, for example as a result of contact of the pad with a human body, there is a risk that the voltage on the bonding pad will increase to a very high value which may seriously damage or even destruct the circuit, the protection diode will break down before the damage has occurred, thus enabling the electric charge to be removed. The operation of the protection diode is enhanced by the “snap-back” effect, whereby the lateral bipolar transistor, formed by the drain region as the collector and the source region and the surface region as, respectively, the emitter and the base, becomes operative.
To ensure a proper operation of the circuit, it is very important that the properties of the protection element, during operation, are not or hardly subject to change as a result of breakdown. An important parameter in this respect is the leakage current of the diode, because too large a leakage current of the protection diode adversely affects the quality of the entire circuit. In practice it has been found that this leakage current can increase considerably. The robustness of the protection element can be increased by providing a resistance in series with the drain, as proposed in the above-mentioned patent U.S. Pat. No. 5,493,142. The resistance provides for a uniform current distribution over the surface of the diode, so that the formation of generation centers as a result of local current concentration can be precluded. A drawback of such a resistance is, inter alia, that during normal operation the current passing through the transistor also runs through the resistance. In order to keep the overall resistance at a sufficiently low level, it is often necessary to reduce the transistor resistance by increasing the transistor, which requires additional space.
SUMMARY OF THE INVENTION
It is an object of the invention to provide, inter alia, an integrated circuit which comprises a robust and compact ESD-protection. To achieve this, a semiconductor device in accordance with the invention is characterized in that the surface area is provided with a well of the same conductivity type as the surface area of the second conductivity type and a higher doping than the surface area, which well extends from the surface to a greater depth in the semiconductor body than the drain region and, viewed on the surface, is situated at a distance from the channel region and extends only below a part of the drain region, said drain region being situated, on the side facing away from the channel region, in the well and, on the side bordering on the channel region, in the surface area with a lower doping.
The invention is based, inter alia, on the realization that in known ESD-protections, electric breakdown generally occurs at the surface, where it gives rise to degradation of the surface and generation of additional surface conditions. In the device in accordance with the invention, breakdown takes place in the bulk of the semiconductor body, at a distance from the surface, near the curvature of the pn-junction between the drain region and the well as a result of the doping in the well. As a result of the bulk-breakdown, the ESD-protection is much more stable than in known devices and, also after breakdown, the leakage current remains at a low level.
A preferred embodiment in which the above-described “snap-back” effect may be used very effectively is characterized in that the well is of the second conductivity type and provided with a surface area of the first conductivity type which is situated at a distance from the drain region of the first conductivity type and which forms the emitter of a lateral bipolar transistor whose base region and collector region are formed, respectively, by the well of the second conductivity type and the drain region of the first conductivity type. When breakdown has occurred at the drain region, this transistor may become conducting and hence remove a substantial part of the electric charge. In this connection, a favorable embodiment is characterized in that the well is provided with a heavily doped contact region of the second conductivity type which is conductively connected to the emitter zone of the first conductivity type, said emitter zone, viewed on the surface, being situated between the collector region and the contact region of the well.
By virtue of the robustness of the above-described ESD-protection, an additional resistance in the current path of the drain region is no longer necessary. A further preferred embodiment offering special advantages, in particular if the transistor forms an output transistor of the circuit, is characterized in that the field effect transistor is LDD-type in which the drain region is provided with a lightly doped region with a length which is determined by a spacer arranged on the side wall of the insulated gate electrode.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
REFERENCES:
patent: 4990976 (1991-02-01), Hattori
patent: 5430595 (1995-07-01), Wagner et al.
patent: 5440162 (1995-08-01), Worley et al.
patent: 5493142 (1996-02-01), Randazzo et al.
patent: 5623156 (1997-04-01), Watt
patent: 5844280 (1998-12-01), Kim
Biren Steven R.
Malsawma Lex H.
Smith Matthew
U.S. Philips Corporation
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