Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-17
2002-11-19
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C257S371000, C257S408000
Reexamination Certificate
active
06483155
ABSTRACT:
This application is based on and claims priority of Japanese patent application 2001-198594, filed on Jun. 29, 2001, the whole contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having pocket regions for suppressing the short channel effect and its manufacture method.
B) Description of the Related Art
With the advent of finer semiconductor devices, there arises a problem of the short channel effect relative to a threshold value of a transistor. As a countermeasure for this problem, a pocket structure has been proposed. In an n-channel MOS transistor, p-type pocket regions are formed under the opposite ends of the gate. Boron (B) is widely used as impurities for forming pocket regions. Indium (In) is also used recently as impurities for forming p-type pocket regions.
An n-channel MOS transistor using indium as the impurities for forming pocket regions has the following advantages:
a large suppression ability of the short channel effect; and
an improved drive capacity.
These advantages may be ascribed to a larger atomic weight (
115
) of indium than that (
11
) of boron, which makes indium atoms difficult to segregate and diffuse.
With reference to
FIGS. 4A
to
4
D, a conventional method of manufacturing a semiconductor device having pocket regions will be described.
As shown in
FIG. 4A
, an isolation region
2
is formed in a principal surface of a silicon substrate
1
. In the structure shown in
FIG. 4A
, an isolation trench is formed in the silicon substrate
1
and filled with insulating material such as silicon oxide. Unnecessary insulating material deposited on the surface of the silicon substrate
1
is removed by chemical mechanical polishing (CMP) or the like to form a shallow trench isolation (STI) structure.
Instead of STI, local oxidation of silicon (LOCOS) may be used for forming an isolation region. The isolation region
2
defines a number of active regions. In the following description, an active region for forming an n-channel MOS transistor is used by way of example.
Boron ions are implanted into the active region of the silicon substrate
1
at an acceleration energy of 300 keV and a dose of about 3.0×10
13
cm
−2
to thereby form a p-type well
3
. Next, boron ions are implanted at an acceleration energy of 30 keV and a dose of about 5.0×10
12
cm
−2
to form a channel region with an adjusted threshold value.
A gate insulating film
4
is formed on the surface of the active region, and a gate electrode layer of polysilicon, polycide or the like is formed on the gate insulating film
4
. The gate electrode layer and gate insulating film are patterned by using a resist mask to form an insulated gate electrode
5
with the gate insulating film
4
.
As shown in
FIG. 4B
, by using the insulated gate electrode as a mask, arsenic (As) ions are implanted at an acceleration energy of 5 keV and a dose of about 3.0×10
15
cm
−2
to form shallow extension regions
6
.
As shown in
FIG. 4C
, pocket regions
7
are formed under the extension regions
6
. For example, indium ions are implanted at an acceleration energy of 100 keV and a dose of about 6.3×10
13
cm
−2
along four directions tilted by
30
degrees from the substrate normal to form indium doped regions
7
.
As shown in
FIG. 4D
, an insulating layer of silicon oxide or the like is deposited covering the insulated gate electrode
5
. The insulating layer is anisotropically etched to leave only side wall spacers
8
on the side walls of the insulated gate electrode
5
.
By using the insulated gate electrode and side wall spacers as a mask, n-type impurities are implanted to form deep source/drain regions
9
. For example, phosphorous (P) ions are implanted at an acceleration energy of 15 keV and a dose of about 5.0×10
15
cm
−2
. The deep source/drain regions
9
are made for forming good contact with metal electrodes. If a silicide layer is formed to lower the resistance of the source/drain regions, compound of metal and silicon is formed on the surfaces of the source/drain regions
9
.
The semiconductor substrate after the ion implantation processes is heated by lamp heating to activate the impurities. For example, the lamp heating is performed at 1025° C. for about 3 seconds.
An n-channel MOS transistor having pocket regions containing indium has the advantages of suppressing the short channel effect and improving the drive capacity. However, junction leak current increases. Leak current of a narrow channel transistor also increases because of the inverse narrow channel effect.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device having n-channel MOS transistors with pocket regions containing indium, the semiconductor device being able to suppress an increase in leak current to be caused by the use of indium.
It is another object of the invention to provide a method of manufacturing a semiconductor device having pocket regions formed by indium ion implantation, the method being able to suppress an increase in leak current to be caused by the use of indium.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a silicon substrate having a principal surface; first and second active regions defined by an isolation region formed in a principal surface of said silicon substrate; a first n-channel MOS transistor comprising a first insulated gate with a gate insulating film formed in said first active region, first extension regions formed in said first active region on both sides of the first insulated gate, and first pocket regions formed in said first active region on both sides of the first insulated gate at a deeper position than the first extension regions, the first pocket regions being doped with indium at a first concentration; and a second n-channel MOS transistor comprising a second insulated gate with a gate insulating film formed in said second active region, second extension regions formed in said second active region on both sides of the second insulated gate, and second pocket regions formed in said second active region on both sides of the second insulated gate at a deeper position than the second extension regions, the second pocket regions being doped with indium at a second concentration lower than the first concentration.
According to another aspect of the invention, there is provided a semiconductor device comprising: a silicon substrate having a principal surface; first and second active regions defined by an isolation region formed in a principal surface of said silicon substrate; a first n-channel MOS transistor comprising a first insulated gate with a gate insulating film formed in said first active region, first side wall spacers formed on both side walls of the first insulated gate, first extension regions formed in said first active region on both sides of the first insulated gate, and first pocket regions formed in said first active region on both sides of the first insulated gate at a deeper position than the first extension regions, the first pocket regions being doped with indium at a first concentration, and said first n-channel MOS transistor including regions of amorphous phase under the first side wall spacers; and a second n-channel MOS transistor comprising a second insulated gate with a gate insulating film formed in said second active region, second side wall spacers formed on both side walls of the second insulated gate, second extension regions formed in said second active region on both sides of the second insulated gate, and second pocket regions formed in said second active region on both sides of the second insulated gate at a deeper position than the second extension regions, the second pocket regions being doped with indium at a second concentration lower than the first concentration, and said second n-channel MOS transist
Okabe Ken-ichi
Wada Hajime
Watanabe Kou
Fujitsu Limtied
Ngo Ngan V.
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