Semiconductor device having plurality of leads

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame

Reexamination Certificate

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C257SE23031

Reexamination Certificate

active

07728412

ABSTRACT:
A method of making a semiconductor device including a semiconductor chip having a plurality of pads, and a lead frame having a plurality of leads. Each of the plurality of leads has a mounting surface for mounting the semiconductor device, a wire connection surface having a thick portion, and a thin portion whose thickness is thinner than the thick portion. The length of each wire connection surface was furthermore formed shorter than the mounting surface, by arranging so that the thin portion of each lead dives below the semiconductor chip, securing the length of the mounting surface of each lead, a distance from the side face of the semiconductor chip to the side face of a molded body of the semiconductor device being shortened as much as possible, and the package size is brought close to chip size, with miniaturization of QFN.

REFERENCES:
patent: 6008068 (1999-12-01), Yamada
patent: 6198171 (2001-03-01), Huang et al.
patent: 6849931 (2005-02-01), Nakae
patent: 6882048 (2005-04-01), Ikenaga et al.
patent: 7109067 (2006-09-01), Kobayashi
patent: 2002/0140061 (2002-10-01), Lee
patent: 2003/0134452 (2003-07-01), Mazzola et al.
patent: 2004/0253764 (2004-12-01), Kang et al.
patent: 2005/0106777 (2005-05-01), Ikenaga et al.
patent: 2003-37219 (2003-02-01), None

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