Semiconductor device having plural memories which synchronously

Details Semiconductor device having plural memories which synchronously Semiconductor device having plural memories which synchronously

1996-03-29

1997-07-01

Nelms, David C.

Static information storage and retrieval

Read/write circuit

365 49, 365233, G11C 700

Patent

active

056445350

ABSTRACT:
A memory access request signal is generated with activation of three different signals, i.e., memory select signal, operating mode signal and operating input signal. When only the memory select signal and operating mode signal are activated, internal operation is not executed, and only an operating mode for determining access allow signal generation timing is determined. The access allow signal is generated at the same timing as the execution of the operating mode.

REFERENCES:
patent: 5184320 (1993-02-01), Dye
patent: 5226009 (1993-07-01), Arimoto
patent: 5226147 (1993-07-01), Fujishima et al.
patent: 5245582 (1993-09-01), Kimura
"QRAM--Quick Access Memory System" Ooba et al; 1990; IEEE; pp. 417-420.

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