Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2001-08-30
2002-11-05
Paladini, Albert W. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S784000, C257S779000, C257S203000, C257S208000
Reexamination Certificate
active
06476505
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a pad arrangement and pad structure of a semiconductor device, and more particularly to a semiconductor pellet having electric pads arranged in a plurality of parallel lines on the periphery thereof.
In the semiconductor device, the electric pads are supplied in order to provide voltage and input-output a signal for functioning as a circuit. The electric pad is electrically connected to a substrate for a ball grid array (BGA) and a lead frame as an input/output terminal of a semiconductor integrated circuit. In order to shorten the distance for wire bonding connection, the electric pads are generally formed on the periphery of the semiconductor pellet. The wire bonding connection is performed using a metal ball made from for example gold pressed to the electric pad. Connecting points are then bridged through the empty space by a thin wire which is then pressed to the lead frame. Thus, the electric pads require a much wider area than the area of the portion in which the metal ball is pressed.
On the other hand, as a result of integrated circuits becoming microscopic, the number of electric pads provided in the semiconductor pellet increases. Because of this, it becomes difficult to arrange the electric pads in a line on the periphery of the semiconductor pellet. To overcome this, the electric pads are arranged in double lines for a semiconductor pellet where many electric pads are provided.
The conventional technology in which the electric pads are arranged in double lines is disclosed in Japanese laid-open-patent No. HEI 2-119233 and HEI 2-186650.
However, in a semiconductor pellet having electric pads with the above described double line structure, when the connecting points between the electric pads and the lead frame or the substrate have been connected electrically by wire bonding, lo there can be a problem where the distance between the thin metal wires of the wire bonding causes short-circuits because of the semiconductor pellet's position, deviation, and so forth.
SUMMARY OF THE INVENTION
The object of the present invention is providing a semiconductor pellet where the thin metal wires do not short-circuit electrically To achieve the above object, the present invention discloses the arrangement of the pads in the semiconductor pellet having a central area and a peripheral area. The semiconductor pullet includes an integrated circuit formed in the central area of the pellet, first electric pads arranged in a line in the peripheral area and second electric pads connected to the conductive lines each of which has a second width L. The first pad has a first width S
1
and arranged with a first interval P The second pads have a third width S
2
and are located outside of the first pads in a parallel line to the line of said first pads with a second interval C. The first, second and third widths S
1
, L, S
2
and the first interval P has the relationship P>S
2
>S
1
+L. Each of the second pads are located at the positions corresponding to the middle positions between the first pads adjoining each other where the second pads are located in a first area which is inside of straight lines from a center of the semiconductor pellet having an angle &thgr; with a side of the semiconductor pellet, in which &thgr;>tan
−1
(2C/(P−S
1
)). Further, each of the second pads are located at the positions shifting in a direction towards a corner of the semiconductor pellet from the middle positions where the second pads are located in a second area which is outside of the first area.
Typical ones of various inventions of the present application have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.
REFERENCES:
patent: 5818114 (1998-10-01), Pendse et al.
patent: 6121690 (2000-09-01), Yamada et al.
patent: 6251768 (2001-06-01), Lin
patent: 2-119233 (1990-05-01), None
patent: 2-186649 (1990-07-01), None
patent: 407297348 (1995-11-01), None
Oki Electric Industry CO Ltd.
Paladini Albert W.
Rabin & Berdo P.C.
Thai Luan
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