Semiconductor device having no cracks in one or more layers...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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Details

C257S750000

Reexamination Certificate

active

07847403

ABSTRACT:
A semiconductor device and a method of manufacturing the same which yields high reliability and a high manufacturing yield. The semiconductor device includes a metal line layer having a plurality of metal line patterns spaced apart from each other, and at least one underlying layer under the metal line layer, wherein the space between two adjacent metal line patterns has a sufficient width to prevent a crack from occurring in one or more of the underlying layers. The cracking of an underlying layer may also be prevented by providing a slit in a direction parallel to the space between two adjacent metal line patterns at a sufficient distance from the space between the two adjacent metal line patterns.

REFERENCES:
patent: 4467345 (1984-08-01), Ozawa
patent: 4835591 (1989-05-01), Matsukawa
patent: 5229642 (1993-07-01), Hara et al.
patent: 5329162 (1994-07-01), Nadaoka
patent: 5382831 (1995-01-01), Atakov et al.
patent: 10-84059 (1998-03-01), None
patent: 10-1999-0026137 (1999-04-01), None
patent: 10-2000-0033091 (2000-06-01), None

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