Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2003-01-10
2004-11-16
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S778000, C257S787000, C438S127000
Reexamination Certificate
active
06818999
ABSTRACT:
BACKGROUND OF THE INVENTION
This application claims the benefit of Japanese Patent Application No. 2002-079240 filed Mar. 20, 2002 in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to semiconductor devices and methods of manufacturing the same, and more particularly to a semiconductor device of MCP (Multi Chip Package) structure in which multiple semiconductor chips are provided in a single package and a method of manufacturing the same.
2. Description of the Related Art
Currently, compact electronic equipment such as mobile devices and the like is becoming smaller, and as a result the components built in to the equipment are also becoming smaller.
Therefore, a semiconductor device of MCP structure, in which multiple semiconductor chips are arranged intensively in a single package, has gained attention as a way to decrease the mounting area of the semiconductor device, which is the main component of such equipment.
FIG.
1
and
FIG. 2
show an example of a conventional semiconductor device of MCP structure. The semiconductor device
1
A shown in
FIG. 1
is configured with multiple (two of which are shown in the figure) semiconductor chips
3
and
4
placed one on top of the other. In other words, the first semiconductor chip
3
is first arranged on top of a substrate
2
, and then the second semiconductor
4
is placed on top of the first semiconductor chip
3
(this type of MCP is referred to as the stack type).
The first and the second semiconductor chips
3
and
4
are electrically connected to the substrate
2
by means of wires
5
. Furthermore, a sealing resin
6
is molded to the substrate
2
and thus the semiconductor chips
3
and
4
as well as the wires
5
are all protected by this sealing resin
6
. Solder balls
7
or the external connecting terminals are arranged on the under surface of the substrate
2
. The solder balls
7
are connected to the wires
5
through wiring and through-holes formed in the substrate
2
.
A semiconductor device
1
B shown in
FIG. 2
is configured with multiple (two of which are shown in the figure) semiconductor chips
3
and
4
arranged next to each other on the substrate
2
in the horizontal direction thereof (this type of MCP is referred to as the plane type). The first and the second semiconductor chips
3
and
4
are electrically connected to the substrate
2
by means of wires
5
. Furthermore, the sealing resin
6
is molded to the substrate
2
, and thus the semiconductor chips
3
and
4
as well as the wires
5
are all protected by this sealing resin
6
. The solder balls
7
or the external connecting terminals are arranged on the under surface of the substrate
2
. The solder balls
7
are connected to the wires
5
through wiring and through-holes formed in the substrate
2
.
The semiconductor chips
3
and
4
on the semiconductor devices
1
A and
1
B of MCP structure are generally manufactured using only the non-defective chips that have been previously tested. However, if the semiconductor chips
3
and
4
to be used are in their early stage of development, or if there is a technical problem on the semiconductor chips themselves, the reliability of the semiconductor device can not be ensured by conducting only the usual test process. An example of this is a memory using the DRAM cell core technique. In such a case, an acceleration test carried out by heating to remove the initial defective semiconductor chips, referred to as the burn-in, is required.
FIG.
3
and
FIG. 4
show manufacturing processes of the conventional semiconductor devices
1
A and
1
B of MCP structure.
FIG. 3
shows the manufacturing processes of the semiconductor devices
1
A and
1
B, and
FIG. 4
shows the processing of each of the manufacturing processes.
In steps S
10
A through S
12
A (a step is represented by S in the figure), the first semiconductor chip
3
is manufactured. In S
10
B through
12
B, the second semiconductor chip
4
is manufactured. To manufacture each of the semiconductor chips
3
and
4
, wafers with each semiconductor chips
3
and
4
are first formed (S
10
A and S
10
B), respectively. Subsequently, dicing is conducted to singularize the wafers into individual semiconductor chips
3
and
4
(S
11
A and S
11
B), thus manufacturing the first and the second semiconductor chips
3
and
4
(S
12
A and S
12
B).
After the first semiconductor chip
3
requiring the burn-in and the second semiconductor chip
4
not requiring the burn-in are manufactured, respectively, the first and the second semiconductor chips
3
and
4
are mounted to the substrate (S
13
). When doing so, the first and the second semiconductor chips
3
and
4
are stacked on the substrate
2
, in the semiconductor device
1
A shown in
FIG. 1
; and the first and the second semiconductor chips
3
and
4
are mounted side by side on the substrate
2
, in the semiconductor device
1
B shown in FIG.
2
.
The wires
5
are then bonded between each of the semiconductor chips
3
and
4
, and the substrate
2
(S
14
). Subsequently, resin sealing is performed on the substrate
2
, and the sealing resin
6
is formed (S
15
). The substrate provided with the sealing resin
6
is then singularized into individual semiconductor devices
1
A and
1
B by dicing (S
16
) thus manufacturing the semiconductor devices
1
A and
1
B (S
17
).
In the semiconductor devices
1
A and
1
B of MCP structure, in which multiple semiconductor chips
3
and
4
are arranged, the semiconductor chip
3
requiring the burn-in and the semiconductor chip
4
not requiring the burn-in may be co-mounted on one of the semiconductor device
1
A or
1
B, as discussed above.
In order to guarantee the reliability of such semiconductor device
1
A or
1
B, it becomes necessary to conduct the burn-in to the semiconductor chip
3
requiring the burn-in. Therefore, in the semiconductor device
1
A or
1
B, where both the semiconductor chip
3
requiring the burn-in and the semiconductor chip
4
not requiring the burn-in co-exist, the burn-in is performed to remove the initially defective ones of the first semiconductor chip
3
(S
18
). Then, the result obtained from the burn-in is evaluated, and if processing failure is found in the first semiconductor chip
3
, the semiconductor device provided with such first semiconductor chip
3
is removed.
Next, a final evaluation test, for example, the electrical property test and the appearance test, is performed (S
20
). If a defective device is found, such device is removed (S
21
). By performing each of the above processes, the semiconductor device can be completed.
However, in a semiconductor device
1
A where the first semiconductor chip
3
and the second semiconductor
4
chip are arranged on the substrate
2
, and sealed by the sealing resin
6
as in the prior art, the performance of the burn-in to the first semiconductor chip
3
causes the heat to also be applied to the second semiconductor chip
4
not requiring the burn-in. Thus, during the burn-in, there is a possibility that the second semiconductor chip
4
deteriorates or is destroyed.
As means to avoid such problems, a method in which the burn-in is performed to the first semiconductor chip
3
, requiring the burn-in, before mounting the first-semiconductor chip
3
to the semiconductor device
1
A or
1
B, i.e., when on the wafer (wafer level burn-in) has been considered. However, even when using such a method, new problems, such as, the necessity of a circuit for wafer level burn-in to be incorporated in each of the semiconductor chips, the necessity of a large wafer level burn-in device, and low through-put arise, and the wafer level burn-in becomes difficult to perform.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide, in view of the above shortcomings, a semiconductor device and a method of manufacturing a semiconductor device that prevent damage to the semiconductor chip not requiring the burn-in while still ensur
Akashi Yuji
Ikuta Takeshi
Kikuma Katsuhito
Elms Richard
Fujitsu Limited
Westerman Hattori Daniels & Adrian LLP
Wilson Christian D.
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