Semiconductor device having multiple-layer hard mask with...

Details Semiconductor device having multiple-layer hard mask with... Semiconductor device having multiple-layer hard mask with...

2011-07-26

2011-07-26

Arora, Ajay K (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Encapsulated

C257SE21488, C438S717000

Reexamination Certificate

active

07986049

ABSTRACT:
A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a thermal process, the difference between the final stresses of the first and second layer becomes smaller, to reduce the likelihood of peeling of the first or second layer. The initial stress of the first layer includes a compressive stress and the initial stress of the second layer includes a tensile stress.

REFERENCES:
patent: 6271592 (2001-08-01), Kim et al.
patent: 2004/0108599 (2004-06-01), Takayama et al.
patent: 2005/0153535 (2005-07-01), Hwang et al.
patent: 6-268077 (1994-09-01), None
patent: 2002-0017832 (2002-03-01), None
patent: 2003-0027795 (2003-04-01), None
patent: 10-2005-0035023 (2005-04-01), None
patent: 10-2006-0010932 (2006-02-01), None
patent: 10-2006-0074995 (2006-07-01), None
patent: 10-0636919 (2006-10-01), None

Affiliated with

Also associated with

Rating

Semiconductor device having multiple-layer hard mask with... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device having multiple-layer hard mask with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having multiple-layer hard mask with... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2628918