Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2011-03-08
2011-03-08
Ngo, Ngan (Department: 2893)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S427000, C438S445000, C257SE21035
Reexamination Certificate
active
07902035
ABSTRACT:
A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.
REFERENCES:
patent: 6252284 (2001-06-01), Muller et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6642090 (2003-11-01), Fried et al.
patent: 6706571 (2004-03-01), Yu et al.
patent: 6858478 (2005-02-01), Chau et al.
patent: 6909147 (2005-06-01), Aller et al.
patent: 7190050 (2007-03-01), King et al.
patent: 7196380 (2007-03-01), Anderson et al.
patent: 7247887 (2007-07-01), King et al.
patent: 7256078 (2007-08-01), Anderson et al.
patent: 7256464 (2007-08-01), Liao et al.
patent: 7265008 (2007-09-01), King et al.
patent: 7382020 (2008-06-01), Liu et al.
patent: 7508031 (2009-03-01), Liu et al.
patent: 7528465 (2009-05-01), King et al.
patent: 7605449 (2009-10-01), Liu et al.
patent: 7612405 (2009-11-01), Yu et al.
patent: 2004/0052948 (2004-03-01), Gronbeck et al.
patent: 2005/0153490 (2005-07-01), Yoon et al.
patent: 2006/0088967 (2006-04-01), Hsiao et al.
patent: 2006/0234456 (2006-10-01), Anderson et al.
patent: 2006/0270181 (2006-11-01), Sandhu et al.
patent: 2007/0099353 (2007-05-01), Thean et al.
patent: 2007/0120156 (2007-05-01), Liu et al.
patent: 2007/0122953 (2007-05-01), Liu et al.
patent: 2007/0122954 (2007-05-01), Liu et al.
patent: 2007/0128782 (2007-06-01), Liu et al.
patent: 2007/0132053 (2007-06-01), King et al.
patent: 2007/0161171 (2007-07-01), Burnett et al.
patent: 2008/0006852 (2008-01-01), Beintner et al.
patent: 2008/0081420 (2008-04-01), Kim
patent: 2008/0128797 (2008-06-01), Dyer et al.
patent: 2008/0230852 (2008-09-01), Yu et al.
patent: 2008/0290470 (2008-11-01), King et al.
patent: 2008/0296632 (2008-12-01), Moroz et al.
patent: 2009/0181477 (2009-07-01), King et al.
patent: 2009/0209074 (2009-08-01), Anderson et al.
patent: 2010/0003802 (2010-01-01), Kim
patent: 2010/0015778 (2010-01-01), Lin et al.
patent: 2010/0038679 (2010-02-01), Chan et al.
Doyle, B.S., et al., “High Performance Fully-Depleted Tri-Gate CMOS Transistors,” IEEE Electron Device Letters, vol. 24, No. 4, Apr. 2003, pp. 263-265.
Shang, H., et al., “Investigation of FinFET devices for 32nm technologies and beyond,” Symposium on VLSI Technology Digest of Technical Papers, 2006, 2 pgs.
Hsu Yu-Rung
Yeh Chen-Nan
Yu Chen-Hua
Ngo Ngan
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
Semiconductor device having multiple fin heights does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having multiple fin heights, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having multiple fin heights will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2647957