Semiconductor device having multilayered metal interconnection s

Details Semiconductor device having multilayered metal interconnection s Semiconductor device having multilayered metal interconnection s

1998-04-23

2000-07-11

Nelms, David

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438599, 438618, 438622, 438624, 438626, 438645, 438780, 438787, 428598, H01L 2144

Patent

active

060872500

ABSTRACT:
A highly reliable semiconductor device having superior flatness and highly precise pattern is obtained. A first metal interconnection 7a is formed on a semiconductor substrate 1. An interlayer insulating film 8a is provided on semiconductor substrate 1 to cover the first metal interconnection 7a. A second metal interconnection 7b is provided on the interlayer insulating film 8a. The interlayer insulating film 8a includes a first silicon oxide film 107a provided on semiconductor substrate 1 to cover the first metal interconnection 7a, and a second silicon oxide film 108a provided to fill concave portions at the surface of the first silicon oxide film 107a. Height of the interlayer insulating film 8a from the surface of the semiconductor substrate 1 is made uniform entirely over one chip.

REFERENCES:
patent: 5278451 (1994-01-01), Adachi et al.
patent: 5362686 (1994-11-01), Harada
patent: 5416359 (1995-05-01), Oda
patent: 5620531 (1997-04-01), Ikai et al.
patent: 5840619 (1998-11-01), Hayashide

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