Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-10-31
2004-12-28
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S773000, C257S775000, C257S758000, C257S211000
Reexamination Certificate
active
06836019
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof, and more particularly, to a semiconductor device having a multilayer interconnection structure and manufacturing method thereof.
2. Description of the Related Art
In general, multilayered interconnection technology employs three-dimensional integrated circuits to more effectively utilize the surface area of the integrated circuits. Highly integrated memory devices having a large capacity equal to or greater than 1 gigabyte, for example, a dynamic random access memory (DRAM) device, can be designed by employing the multilayered interconnection technology.
In multilayer interconnections, active devices and interconnections have a structure in which layers are stacked, and each layer is connected by an interlevel, or interlayer, connection path such as a “plug” or “stud”. Also, a “landing pad” or “tab” for assisting the alignment of the plug is formed on an underlying layer to serve as a target for a plug. Further, the landing pad is connected to an underlying circuit or interconnection, and its surface area is formed to be larger than that of the underlying circuit or interconnection. This results in a larger tolerance of the target for the plug. However, a conventional landing pad or tap assists the alignment of the plug, and due to the line width being larger than that of the stud (or plug), there is a high risk that a short-circuit may occur between neighboring circuit patterns. Thus, at present, instead of using the landing pad, a technology in which self-aligned metal interconnections are formed by an etch stopper has been suggested.
FIG. 1
is a sectional view of a conventional multilayer metal interconnection structure including a stud and an etch stopper, as disclosed in U.S. Pat. No. 5,891,799. Referring first to
FIG. 1
, a metal interconnection
102
is formed on a semiconductor substrate
100
. A first interlevel dielectric (ILD) layer
104
composed of silicon dioxide (SiO
2
) and a first etch stopper
106
composed of silicon nitride (Si
3
N
4
) are sequentially formed on the semiconductor substrate
100
on which the metal interconnection
102
is formed. Next, lower stud holes
108
a
and
108
b
are formed by patterning the first etch stopper
106
and the first ILD layer
104
to expose the metal interconnection
102
and the semiconductor substrate
100
. Next, the lower stud holes
108
a
and
108
b
are filled with a metal material to form lower studs
110
a
and
110
b
. A second ILD layer
112
and a second etch stopper
114
are sequentially formed on the resultant of the semiconductor substrate
100
on which the lower studs
110
a
and
110
b
are formed. Next, upper stud holes
116
a
and
116
b
are formed by etching the second etch stopper
114
and the second ILD layer
112
to expose the lower studs
110
a
and
110
b
. Here, during an etching process for forming the upper stud holes
116
a
and
116
b
, the first etch stopper
106
serves as an etching reference. Next, upper studs
118
a
and
118
b
are formed in the upper stud holes
16
a
and
116
b.
However, the following problems arise in a conventional multilayer interconnection structure. First, in the mentioned prior art, a landing pad is not used. Thus, even though the first etch stopper
106
is used, there is a high risk that misalignment between the lower studs
110
a
,
110
b
and the upper studs
118
a
,
118
b
may occur. Meanwhile, when the landing pad is used, as described above, the distance between patterns decreases. Thus, a short-circuit can readily occur between neighboring conductive patterns.
Furthermore, a bit line of the DRAM is often used as a local interconnection on a peripheral region on which a sense amplifier is formed. In particular, since circuit layers are very densely arranged on the peripheral region, it is not easy to secure a safe distance between patterns in the horizontal direction that are formed on the same level.
Also, since the first and second etch stoppers
106
and
114
composed of silicon nitride (Si
3
N
4
) are formed on the entire resultant of the semiconductor substrate
100
, excessive stress causing circuit distortion occurs in the ILD layers. Furthermore, the first and second etch stoppers
106
and
114
prevent impurities such as carbon (C), fluorine (F), and chlorine (Cl), which are contained in the ILD layers, from being outgassed during a subsequent high temperature heating process. Also, the remaining etch stoppers
106
and
114
disturb the introduction of H
2
and O
2
during a thermal process for reducing dangling bonds between the semiconductor substrate
100
and a gate insulating layer (not shown). As a result, the adhesion characteristics between the semiconductor substrate
100
and the gate insulating layer are adversely affected.
SUMMARY OF THE INVENTION
To address the above limitations, it is a first objective of the present invention to provide a semiconductor device capable of preventing short-circuits between neighboring conductive patterns in highly integrated circuits.
It is a second objective of the present invention to provide a semiconductor device capable of obtaining a sufficient contact margin between upper and lower studs.
It is a third objective of the present invention to provide a semiconductor device capable of preventing short-circuits between neighboring conductive patterns while obtaining a sufficient contact margin between upper and lower studs.
It is a fourth objective of the present invention to provide a semiconductor device capable of reducing stress of an interlevel dielectric (ILD) layer, caused by an etch stopper.
It is a fifth objective of the present invention to provide a semiconductor device capable of adequate outgassing of impurities while reducing stress in circuits.
It is a sixth objective of the present invention to provide a semiconductor device capable of preventing deterioration of the adhesion characteristics of a gate insulating layer and a semiconductor substrate.
It is a seventh objective of the present invention to provide a method for manufacturing the semiconductor device.
Accordingly, to achieve the first through sixth objectives, according to an aspect of the present invention, there is provided a semiconductor device. An interlevel dielectric (ILD) layer is formed on the semiconductor substrate. A first contact stud is formed in the ILD layer having a line width at an entrance portion adjacent the surface of the ILD layer larger than the line width of a contacting portion adjacent the semiconductor substrate. A second contact stud spaced apart from the first contact stud is formed in the ILD layer. It is preferable that the entrance part of the first contact stud has a line width about 30-60% larger than that of the contacting part.
Accordingly, to achieve the first through sixth objectives, according to another aspect of the present invention, there is provided a semiconductor device. An interlevel dielectric (ILD) layer is formed on the semiconductor substrate. A first contact stud having a line width of an entrance part adjacent to the surface of the ILD layer larger than the line width of a contacting part adjacent to the semiconductor substrate is formed in the ILD layer. A second contact stud spaced apart from the first contact stud is formed in the ILD layer. A landing pad having a line width larger than that of the second contact stud is formed on the ILD layer to contact the surface of the second contact stud.
It is preferable that the second contact stud has the line width of a contacting part that is entirely the same as that of an entrance part, and the entrance part of the first contact stud has a line width about 30-60% larger than that of the contacting part.
Accordingly, to achieve the first through sixth objectives, according to still another aspect of the present invention, there is provided a semiconductor device. An interlevel dielectric (ILD) layer is formed on the semiconductor substrate. A first contact stud ha
Jeong Hong-sik
Kim Ki-nam
Yang Won-suk
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
Tran Minhloan
Tran Tan
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