Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent
1993-06-29
1995-02-21
James, Andrew J.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
257734, 257759, 257760, 257765, 257773, 257774, 257776, H01L 2348, H01L 2946, H01L 2954, H01L 2962
Patent
active
053919211
ABSTRACT:
A semiconductor device that has a feature in the spatial relationship between the wiring in a multi-level wiring and the intermediate insulating films. In the lower part of the second and/or subsequent levels of wiring there exist intermediate insulating films that have a pattern which is the same as the pattern of the wiring. Because of this arrangement, the intermediate insulating film does not exist between the wiring on the same level. The first structure of the multi-level wiring has the intermediate insulating films formed in wall-like shape, with the lower end of the intermediate insulating films reaching an underlying insulating layer formed on the surface of the semiconductor substrate. The second structure of the multi-level wiring is a quasi air gap metallization structure. As a result of realization of such structures, in the semiconductor device according to the present invention, the parasitic capacitance due to the coupling capacitances between the wiring can be reduced compared with a semiconductor device that has a structure in which the spaces between the wiring are filled with the intermediate films.
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R. L. M. Dang et al., "Coupling Capacitances for Two-Dimensional Wires", IEEE Electron Device Letters, vol. EDL-2, No. 8, Aug. 1981, pp. 196-197.
Y. Ushiku et al., "A Three-Level Wiring Capacitance Analysis for VLSIs Using a Three-Dimensional Simulator", IEDM 88, pp. 340-343.
Katoh Takuya
Kudoh Osamu
Okada Kenji
Shiba Hiroshi
James Andrew J.
Jr. Carl Whitehead
NEC Corporation
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