Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-13
2004-09-28
Thomas, Tom (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S328000, C257S329000, C257S330000, C257S331000, C257S332000, C257S621000
Reexamination Certificate
active
06798018
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having an insulated gate power MOSFET in which a gate electrode is formed in a recessed trench formed from the surface of a semiconductor layer, so-called transistor cells of a trench structure are arranged in a matrix form. More specifically, the invention relates to a semiconductor device having a MOSFET improved in gate dielectric breakdown voltage by forming a gate pad contacted with a gate wiring inside a recessed part etched from the semiconductor layer surface as similar to the recessed trench formed with the gate electrode.
A high-power gate-driven MOS transistor of a traditional trench structure adopts a structure where many transistor cells are arranged in a matrix form for the realization of heavy current. For example, as shown in
FIG. 8A
of a partially sectional illustration, an n-type semiconductor layer (epitaxial growth layer)
21
to be a drain region is epitaxially grown over an n
+
-type semiconductor substrate
21
a.
A recessed trench is formed in the semiconductor layer
21
in a grid form. A gate oxide
24
is deposited over the inner surface, and polysilicon to be a gate electrode
25
is buried. Then, a p-type channel diffusion region
22
is formed in the semiconductor layer
21
therearound, and an n
+
-type source region
23
is formed around on the gate electrode
25
side, whereby a channel region
22
a
is formed vertically as having contact with the gate oxide
24
. Furthermore, a contact hole is formed in an insulating film
26
comprised of SiO
2
; the insulating film is formed over the surface. A source wiring
27
is formed so as to have Ohmic contact with the exposed source region
23
and channel diffusion region
22
. A drain electrode
28
is formed on the backside of the semiconductor substrate
21
a.
The gate electrode
25
described above is comprised of polysilicon and is not formed into fully low resistance. Therefore, as depicted in
FIG. 8B
of a plan illustration showing an example of a gate wiring
29
of a semiconductor chip, it is formed in which the gate wiring of a metal film comprised of A
1
is partially connected around a transistor cell region
30
or inside the cell region
30
so as not to increase resistance in cells remote from a wire bonding part
29
a
. To contact the polysilicon film with the metal film formed of Al, as shown in
FIG. 8C
of a partially sectional illustration showing the portion of the gate wiring
29
, a gate pad
25
a
is formed on the semiconductor layer surface continuously to the gate electrode
25
through a gate oxide (not shown). The gate wiring
29
is formed above the gate pad
25
a
through an insulating film
31
(the insulating film is also formed on the left side in the drawing, but it is omitted in the drawing). In addition, as shown in
FIG. 8B
, there is also the case where the gate wiring called a gate finger
29
b
is disposed in the cell region
30
in places, but the case has the same structure as well. In
FIG. 8B. 27
a
denotes a wire bonding portion of the source wiring.
Furthermore, a plan structure of a cell surrounded by the gate electrodes in the transistor cells is formed into an arbitrary shape such as a square, pentagon or hexagon. Moreover, in these transistors, they are often connected to an inductive load such as a motor. In this case, a reverse electromotive force might be applied when the operation is turned off. To prevent the transistors from being destroyed, such a method is adopted that the source electrode
27
is also connected to the channel diffusion region
22
as described above, whereby a reverse protection diode is formed between the source and the drain.
As set forth, in the MOSFET of the trench structure, the gate pad
25
a
connected to the gate wiring
29
is formed over the semiconductor layer surface through the gate oxide. Thus, it is positioned higher than the gate electrode
25
formed inside the recessed trench, and the gate pad
25
a
formed continuously to the gate electrode
25
is passed through a corner part of the recessed trench as indicated by A shown in FIG.
8
C. Usually it is difficult to form an oxide film in a corner part and a resultant film becomes thinner in general, and thus problems arise such that the gate pad is short-circuited with the semiconductor layer, or gate voltage is dropped. On this account, the corner part undergoes a process called a rounding process, that is, a process for rounding the corner part in order to sufficiently deposit the gate oxide over the corner part as well. Even so, voltage cannot be enhanced enough. As for the process for rounding the corner part, a process in which sacrifice oxidation is performed to remove the oxide film in order to remove the semiconductor layer roughened after etching such as reactive ion etching; sacrifice oxidation is performed at a high temperature of about 1100° C. (generally, about 900° C.) to form a thick oxide film and remove it.
Additionally, in this type of semiconductor device, it is also necessary to sufficiently be protected from surges particularly.
Furthermore, it has been desired that signals can be transmitted to the surrounding transistor cells in low resistance without disposing the gate fingers, many cells can be formed as many as possible, and ON resistance can be reduced to realize heavy current.
Moreover, in the semiconductor device having many transistor cells of this type arranged in a matrix form, a problem arises that electric fields tend to concentrate on transistor cells around outside the cell region for easy destruction.
SUMMARY OF THE INVENTION
The present invention has been made to solve these problems. The purpose of the present invention is to provide a semiconductor device having a structure capable of sufficiently increasing gate voltage even in such a semiconductor device in which many transistor cells of a trench structure are formed in a matrix form and the gate electrodes thereof are contacted with a gate wiring formed of a metal film.
Another purpose of the present invention is to provide a semiconductor device having a structure that enhances voltage by a trench structure and is hardly broken down in case of a surge.
Still another purpose of the present invention is to provide a semiconductor device having a structure that reduces gate wirings as few as possible and allows signals to be transmitted to each of cells evenly.
Yet another purpose of the present invention is to provide a semiconductor device having a high-power MOSFET that enhances voltage by a trench structure, increases the number of cells as many as possible and realizes heavy current.
Yet another purpose of the present invention is to provide a semiconductor device having a structure where a depletion layer of a pn junction in a cell region is extended to the outer peripheral part of a chip to enhance voltage thereof enhanced even though a gate pad is formed inside a recessed part.
A semiconductor device according to the present invention has a semiconductor layer; a recessed trench formed in the semiconductor layer so as to arrange transistor cells of a trench structure in a matrix form; a gate electrode disposed inside the recessed trench through a gate oxide film; a gate pad disposed continuously to the gate electrode; and a gate wiring comprised of a metal film, the gate wiring disposed being contacted with the gate pad, wherein the gate pad is disposed inside a recessed part formed in the same depth of the recessed trench.
By this structure, the gate pad is formed at a low position inside the recessed part (so-called a sink pad). Thus, the gate electrode formed inside the recessed trench and the gate pad contacted with the gate wiring are continuously formed with no steps, and even the gate pad formed over the semiconductor layer surface through a thin gate oxide film is formed with the gate oxide film in firm thickness with no corners, allowing sufficiently high gate voltage to be obtained. Consequently, a semiconductor device having sufficiently high gate volt
Kitaguro Koichi
Takada Hiroki
Takaishi Masaru
Lee Eugene
Rabin & Berdo P.C.
Rohm & Co., Ltd.
Thomas Tom
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