Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Patent
1997-07-16
1999-05-11
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
H01L23/58
Patent
active
059030119
ABSTRACT:
An object of this invention is to provide a semiconductor device having a monitor pattern which can more strictly ensure the precise finish dimension of a semiconductor integrated circuit device. According to this invention, in a semiconductor device in which a first monitor pattern for monitoring a variation in the dimension of the pattern of the semiconductor integrated circuit device is formed on a semiconductor substrate, the first monitor pattern includes a first SDG region pattern formed on the semiconductor substrate a second SDG region pattern formed on the semiconductor substrate, at least one first gate wiring pattern formed on the first and second SDG region patterns a third SDG region pattern having an area different from the area of the first SDG region pattern and formed on the semiconductor substrate a fourth SDG region pattern having an area different from the area of the first SDG region pattern and formed on the semiconductor substrate and at least one second gate wiring pattern formed on the third and fourth SDG region patterns.
REFERENCES:
patent: 5059899 (1991-10-01), Farnworth et al.
patent: 5598010 (1997-01-01), Uematsu
patent: 5637186 (1997-06-01), Liu et al.
Hughes William
Kabushiki Kaisha Toshiba
Thomas Tom
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