Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-08
2002-04-23
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S349000, C257S346000
Reexamination Certificate
active
06376879
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device that has MISFETs, each having a gate electrode and an insulating film called “side wall” on the sides of the gate electrode. More particularly, the invention relates to an integrated circuit that operates with at least two operating voltages, such as a flash EEPROM which operates with an input voltage generated outside the chip externally applied and a high voltage generated inside the chip.
FIG. 1
shows a conventional MISFET.
A gate insulating film
12
is formed on the semiconductor substrate
11
. A gate insulating film
13
is formed on the gate insulating film
12
. An insulating film
14
called “side wall” is provided on the sides of the gate insulating film
12
. Diffusion layers
15
a
, which have a low impurity concentration and known as “LDDs (Lightly Doped Drains),” are formed in those parts of the substrate
11
which lie beneath the side wall
14
.
Beside the diffusion layers
15
a
, diffusion layers
15
b
are formed which have a higher impurity concentration than the diffusion layers
15
a
. A pre-metal dielectric
16
is formed on the substrate
11
, covering all other parts of the MISFET. The pre-metal dielectric
16
has a contact hole
17
, which reaches one of the diffusion layers
15
b
. The contact hole
17
is filled with a contact plug
18
made of, for example, tungsten (W). A metal wire
19
is provided on the contact plug
18
.
For any LSI having MISFETs described above, the margin between the gate electrode
13
and contact hole
17
of each MISFET is one of the obstacles to the desired increase of integration density. Self-alignment contact (SAC) technique has been proposed as means for reducing the margin between the gate electrode
13
and the contact hole
17
, thereby to enhance the integration density of the LSI.
FIG. 2
illustrates a conventional MISFET to which the self-alignment contact technique has been applied.
As shown in
FIG. 2
, a gate insulating film
12
is provided on the semiconductor substrate
11
. A gate electrode
13
is formed on the gate insulating film
12
. On the gate electrode
13
, a cap insulating film
20
is provided which works as a mask in the process (etching) of making a contact hole
17
. An insulating film
14
called “side wall” is provided on the sides of the cap insulating film
20
. The side wall
14
also functions as a mask in the process (etching) of making the contact hole
17
.
Diffusion layers
15
a
, which have a low impurity concentration and known as “LDDs,” are formed in those parts of the substrate
11
which lie beneath the side wall
14
. Beside the diffusion layers
15
a
, diffusion layers
15
b
are formed which have a higher impurity concentration than the diffusion layers
15
a
. A premetal dielectric
16
is formed on the substrate
11
, covering all other parts of the MISFET. The pre-metal dielectric
16
has the contact hole
17
, which reaches one of the diffusion layers
15
b
. The contact hole
17
is filled with a contact plug
18
made of, for example, tungsten (W). A metal wire
19
is provided on the contact plug
18
.
The MISFET shown in
FIG. 2
is characterized in the following respects.
First, the side wall
14
and the cap insulating film
20
function as a mask in the process of making the contact hole
17
. That is, the side wall
14
, pre-metal dielectric
16
and cap insulating film
20
are made of such materials that the selectivity R
2
/R
1
, or the ratio of the etching rate R
2
of the pre-metal dielectric
16
to the etching rate R
1
of the side wall
14
and cap insulating film
20
, is as high as possible. If the pre-metal dielectric
16
is made of, for example, silicon oxide film (e.g., BPSG film or the like), the side wall
14
and cap insulating film
20
will be made of silicon nitride film.
Second, the gate electrode
13
is always insulated from the contact plug
18
made in the contact hole
17
. This is because the side wall
14
and cap insulating film
20
function as an etching mask even if the gate electrode
13
happens to overlap the contact hole
17
. Thus, the margin between the gate electrode
13
and the contact hole
17
much decreases, serving to enhance the integration density of the LSI.
To enhance the integration density of an LSI having MISFETs to which the self-alignment contact technique (
FIG. 2
) has been applied, it is required that the side wall
14
have a minimum thickness necessary to maintain the gate electrode
13
and the contact plug
18
insulated from each other. If the side wall
14
has such a minimum thickness, the contact plug
18
can be located sufficiently close to the gate electrode
13
(or can overlap the gate electrode
13
) as shown in FIG.
3
. Further, contact plug
18
can have an adequate contact area (proportional to distance Sa) with one of the diffusion layers
15
b
as depicted in FIG.
3
.
As shown in
FIG. 4
, however, the MISFETs may differ in the thickness of the side wall
14
in the course of processing the wafer. The side walls
14
of some MISFETs may be thicker than is desired. If the contact plug
18
is located sufficiently close to the gate electrode
13
, the contact area (proportional to distance Sa) at which the contact plug
18
contacts the diffusion layers
15
b
will become too small. This would increase the contact resistance at the interface between the contact plug
18
and one of the diffusion layers
15
b.
FIG. 5
shows a semiconductor device that has two MISFETs sharing a diffusion layer
15
bb
. The shorter the distance between the gate electrodes
13
of the MISFETS, the smaller the contact area (proportional to distance Sc) between the diffusion layer
15
bb
and the contact plug
18
. The side walls
14
of the two MISFETS, which cover the gate electrodes
13
thereof, may therefore contact each other as shown in FIG.
6
. If this occurs, the contact hole
17
cannot reach the surface of the semiconductor substrate
11
.
The side wall formed on the side of the gate electrode
13
of each MISFET serves not only to achieve a self-alignment contact, but also to form diffusion layers
15
a
and
15
b
of LD structure. The diffusion layers
15
a
and
15
b
of LDD structure perform various functions, such as increasing of the breakdown voltage of the p-n junction of the MISFET, mitigating of the generation of hot carriers, and inhibiting of short-channel effect.
Integrated circuits that operate with two or more operating voltages have MISFETs operating at a low voltage and MISFETs operating at a high voltage. In each MISFET operating at the low voltage, the side wall provided on the sides of the gate electrode is made as thin as possible, thereby forming short LDDS. Further, the contact hole reaching the source/drain diffusion layer is located as close as possible to the gate electrode, thereby to enhance the integration density of the LSI.
In each MISFET operating at the high voltage, the side wall provided on the sides of the gate electrode is made as thick as possible, thereby forming long LDDS. Having long LDDS, the MISFET can operate normally even if a high voltage is applied to it.
In order to enhance the integration density of the LSI and also to make the MISFETs operate normally, it is necessary to form MISFETs of at least two types, different in terms of the LDD length, in a single chip. To this end, however, it has hitherto been necessary to form two or more types of side walls, each type for the MISFETs having one LDD length. As a consequence, photo engraving process (PEP) must be repeated as many times as the types of MISFETs required, in the course of processing the wafer.
In other words, an increased number of steps must be carried out to process the wafer, inevitably increasing the cost of manufacturing the LSI. In view of this, it has been impossible, in practice, to form MISFETs of two types, different in terms of LDD length, in a single chip.
FIG. 7
shows a NOR-type flash EEPROM comprising MISFETS. The memory cells arranged in the memory cell area will be described first.
Eac
Isobe Kazuaki
Mori Seiichi
Takebuchi Masataka
Watanabe Toshiharu
Banner & Witcoff Ltd
Kabushiki Kaisha Toshiba
Meier Stephen D.
LandOfFree
Semiconductor device having MISFETs does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having MISFETs, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having MISFETs will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2869012