Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1997-05-23
1999-07-06
Whitehead, Jr., Carl
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257301, 257775, 257734, H01L 2348, H01L 2352
Patent
active
059201240
ABSTRACT:
A semiconductor device having a structure of at least two interconnect levels is disclosed wherein word lines as a lower interconnect layer are not removed if a misalignment exists when contact holes are formed. The word lines (2) serving as gate electrodes are arranged on a surface of a p-type Si substrate (14) serving as a base. An etching stopper underlay insulative film (10) is formed over the word lines (2), and an etching stopper film (9) is formed to cover the etching stopper underlay insulative film (10). An interlayer insulative film (8) and bit lines (1) are deposited on the etching stopper film (9), and a hole is formed. A sidewall insulative film (16) is formed on a side surface of the hole. The etching stopper film (9) functions to prevent part of the word lines (2) which is located in the hole from being removed.
REFERENCES:
patent: 5336917 (1994-08-01), Kohyama
patent: 5409855 (1995-04-01), Jun
patent: 5489546 (1996-02-01), Ahmad et al.
patent: 5492849 (1996-02-01), Park
Jr. Carl Whitehead
Mitsubishi Denki & Kabushiki Kaisha
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