Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-02-08
2001-11-20
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S683000
Reexamination Certificate
active
06319805
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including an MOS transistor and manufacturing method thereof. More specifically, the present invention relates to a semiconductor device having a metal silicide film for reducing resistance in source/drain regions, and to manufacturing method thereof.
2. Description of the Background Art
In order to improve performance and speed of operation of a semiconductor device, lower resistance and lower capacitance of interconnections have been pursued. As means for reducing resistance, a technique for forming a metal silicide film on a surface of source/drain regions of an MOS transistor has been developed. In the following, an N channel MOS transistor (hereinafter referred to as an NMOS transistor) will be described as an example, for convenience.
FIG. 34
is a cross section showing a conventional MOS transistor. Referring to
FIG. 34
, on a main surface of a silicon substrate
1
, element isolating oxide films
2
are formed selectively. In an active region surrounded by element isolating oxide film
2
on the main surface of silicon substrate
1
, N
−
source/drain regions
7
,
7
are formed, space by a prescribed distance to sandwich a channel region therebetween. N
−
source/drain regions
7
and N
+
source/regions
8
provide source/drain regions having LDD structure. On the channel region, a gate electrode
4
of polycrystalline silicon film is formed with a gate insulating film
3
posed therebetween. On gate electrode
4
, a tungsten silicide (WSi
2
) film
5
is formed in order to reduce resistance of gate electrode
4
. An oxide film
6
is formed to cover gate electrode
4
and tungsten silicide film
5
. On N
+
source/drain regions
8
, a titanium silicide (TiSi
2
) film
9
for reducing resistance of N
+
source/drain regions
8
is formed. An interlayer insulating film
10
is formed to cover the entire surface, and contact holes are provided at prescribed regions of interlayer insulating film
10
. An aluminum interconnection
11
is formed in the contact hole to be electrically connected to titanium silicide film
9
.
When a circuit having a prescribed function is to be formed by arranging MOS transistors such as described above on one chip, an MOS transistor having a desired resistance value is formed by setting the thicknesses of tungsten silicide film
5
and titanium silicide film
9
to desired values.
FIG. 35
is a cross section showing another conventional MOS transistor. Referring to
FIG. 35
, different from the conventional MOS transistor shown in
FIG. 34
, in this another MOS transistor, the silicide film formed on gate electrode
4
is the same silicide film as the titanium silicide film
9
formed on N
+
source/drain regions
8
.
FIG. 36
is a cross section showing a still further conventional MOS transistor. Referring to
FIG. 36
, the MOS transistor is formed on an SOI substrate. The SOI substrate refers to a structure which includes an insulating layer inside the silicon substrate and a single-crystal silicon layer on the insulating layer. When a semiconductor element such as MOS transistor is formed on the SOI substrate, the speed of operation of the apparatus can be increased and short channel effect can be suppressed, because of reduced parasitic capacitance and increased current driveability. The structure including the MOS transistor formed on the SOI substrate will be referred to as an SOI/MOS transistor. Referring to
FIG. 36
, in the SOI/MOS transistor, a buried oxide film
12
is formed on silicon substrate
1
. On the buried oxide film
12
, a single-crystal silicon layer (hereinafter referred to as an SOI layer)
13
is formed.
FIG. 37
is a cross section showing still further conventional SOI/MOS transistor. Referring to
FIG. 37
, in this example, titanium silicide film
9
formed on N
−
source/drain regions
8
is also formed on gate electrode
4
.
Now, when a circuit having a prescribed function is to be provided by arranging the bulk MOS transistor such as shown in
FIGS. 34 and 35
or SOI-MOS transistor such as shown in
FIGS. 36 and 37
, the MOS transistor having a desired resistance value is formed by setting the thicknesses of tungsten silicide film
5
and titanium silicide film
9
in accordance with the circuit characteristic. More specifically, when the resistance value of gate electrode
4
should be different from the resistance value of N
+
source/drain regions
8
, in the above described conventional examples, tungsten silicide film
5
may be formed on gate electrode
4
and titanium silicide film
9
may be formed on N
+
source/drain regions
8
.
Tungsten silicide film
5
and titanium silicide film
9
have different specific resistances, and they are formed through separate process steps. Therefore, it is possible to form these films to have different thicknesses. More specifically, tungsten silicide film
5
is formed by deposition through sputtering followed by patterning. Meanwhile, titanium silicide film
9
is formed by covering periphery of gate electrode
4
with an oxide film
6
, applying titanium on the entire surface, and by turning it into silicide by 2 steps annealing, and thus the titanium silicide film can be formed in self-aligned manner only at an exposed region of the silicon.
Meanwhile, when the gate electrode
4
and N
+
source/drain regions
8
should have the same resistance value, titanium silicide film
9
may be formed both on the gate electrode
4
and on N
+
source/drain regions
8
through the same process steps. In that case, titanium silicide film
9
is formed in self-aligned manner only at the exposed region of silicon, by covering sidewall portions of gate electrode
4
with sidewall oxide film, applying titanium on the entire surface and by performing 2 steps annealing.
In the conventional bulk MOS transistors and SOI/MOS transistors, what is formed on the source region and the drain region is the titanium silicide film
9
of the same thickness. Therefore, the source region cannot have a resistance value which is different from that of drain region.
In order to reduce the resistance value of source/drain regions, thicker silicide film is preferred. However, when the silicide film is made thicker, stress at the silicide/silicon interface increases accordingly, increasing possibility of generation of crystal defects. In order to suppress generation of crystal defects, the silicide film should be made thinner. However, conventionally, the silicide film is made rather thick, in order to reduce resistance value at the source/drain regions. In this case, in order to prevent leakage current derived from the crystal defect at the source/drain junction surface, the depth of the source/drain junction surface has been made deeper so as to prevent influence of the crystal defect. In order to suppress short channel effect of the MOS transistor, it is necessary to form the source/drain junction surface at a shallower portion. However, in the conventional structure in which the silicide film is made thick to reduce the resistance values at the source/drain region, the source/drain junction surface could not be formed at a shallower portion.
Further, in the conventional SOI/MOS transistor, the substrate is in electrically floating state. Therefore, holes generated by impact ionization are accumulated in the substrate, increasing substrate potential. This results in lower potential barrier on the side of the source, which leads to lower breakdown voltage between the source/drain.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device in which source region and drain region can have different resistance values.
Another object of the present invention is to provide a semiconductor device in which source/drain breakdown voltage can be improved.
Another object of the present invention is to provide a method of manufacturing a semiconductor device in which source region and drain region have
Inoue Yasuo
Iwamatsu Toshiaki
Nishimura Tadashi
Yamaguchi Yasuo
Booth Richard
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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