Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2001-02-05
2003-05-13
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S063000
Reexamination Certificate
active
06563748
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a structure for increasing the speed of operations and implementing low power consumption.
2. Description of the Prior Art
As shown in
FIG. 68
, a conventional dynamic random access memory having a shared sense amplifier system comprises memory cell blocks M
1
, M
2
, . . . , Mn and sense amplifier zones YS
1
, YS
2
, . . . , YSn+1 arranged to hold the respective memory cell blocks therebetween. Each memory cell block includes a plurality of memory cells arranged in the form of a matrix, a plurality of word lines arranged in correspondence to rows and a plurality of bit lines arranged in correspondence to columns.
As shown in
FIG. 69
, each sense amplifier zone includes sense amplifiers SA arranged in correspondence to bit lines and selection gates for selectively coupling the sense amplifiers SA with memory cell blocks. Each selection gate is formed by NMOS transistors NA and NB. Symbols BL
11
, /BL
11
, BL
12
, /BL
12
, BL
13
and /BL
13
denote the bit lines of the memory cell block M
1
, symbols BL
21
, /BL
21
, BL
22
, /BL
22
, BL
23
and /BL
23
denote the bit lines of the memory cell block M
2
, symbols BL
31
, /BL
31
, BL
32
, /BL
32
, BL
33
and /BL
33
denote the bit lines of the memory cell block M
3
, and symbol G(i,j) denotes the selection gates respectively.
The respective selection gates are switched in response to gate control signals BLI(
1
,
1
), BLI(
2
,
0
), BLI(
2
,
1
), BLI(
3
,
1
), . . . . Switching of the selection gates is controlled for selectively coupling one of two memory cell blocks with the sense amplifier zone held between the two memory cell blocks.
“Ultra LSI Memory” (Kiyoo Ito, Baifukan, 1994, pp. 161-163) describes methods of driving shared sense amplifiers in detail. The following two methods are employed for driving shared sense amplifiers: Referring to
FIGS. 70 and 71
, symbol BLI(i,j) (j=0 or 1) denotes a gate control signal corresponding to a selected memory cell block Mi, and symbols BLI(i+1,0) and BL(i−1,1) denote gate control signals controlling coupling between sense amplifier zones coupled with the memory cell block Mi and memory cell blocks Mi+1 and Mi−1 respectively.
In the first method, the gate control signals are set to a step-up power supply voltage level (Vpp), an internal power supply voltage level (Vcc) or a ground voltage level (GND) (three-valued control system), where Vpp>Vcc>GND.
As shown in
FIG. 70
, all gate control signals are set to the internal level Vcc in a standby period, for example. In an active period for coupling the memory cell block Mi with the sense amplifier zones, the gate control signal BLI(i,j) corresponding to the selected memory cell block Mi is set to the level Vpp while the gate control signals BLI(i+1,
0
) and BLI(i−1,
1
) corresponding to the non-selected memory cell blocks are set to the level GND.
In the second method, the gate control signals are set to the level Vpp or the level GND (two-valued control system). As shown in
FIG. 71
, all gate control signals are set to the level Vpp in a standby period, for example. In an active period, the gate control signals BLI(i+1,
0
) and BLI(i−1,
1
) are set to the level GND while keeping the gate control signal BLI(i,j) at the level Vpp.
The gate control signals are controlled in the aforementioned manner, for coupling pairs of bit lines of the selected memory cell block with the sense amplifiers SA included in the sense amplifier zones. The other memory cell blocks sharing the sense amplifier zones are disconnected from the sense amplifier zones.
Thus, it follows that data of the selected memory cell block is output to a data input/output line or data of the data input/output line is written in the selected memory cell block. The number of sense amplifier zones can be halved by employing the shared sense amplifier system, thereby reducing the chip area.
Coupling
on-coupling between a memory cell block and a sense amplifier zone is decided by rise/fall of a gate control signal. In order to speed-up the access time, therefore, the gate control signal must be transmitted at a high speed.
However, the gate control signal must drive a large number of (1000 to 4000) selection gates, leading to a large load capacitance of a wire (hereinafter referred to as a BLI wire) transmitting the gate control signal. Further, such a plurality of selection gates are dispersively arranged on the BLI wire over a long distance. According to the conventional structure, therefore, transmission delay of the gate control signal is so remarkable that the access time is retarded.
In addition, power consumption in a circuit (BLI generation circuit) generating the gate control signal is increased by charging/discharging the large load capacitance. This circuit consumes current as to an internally generated step-up power supply voltage Vpp. Thus, it follows that load current is generated in a Vpp generation circuit for generating the step-up power supply voltage Vpp. Therefore, current consumption in the Vpp generation circuit or the area of the Vpp generation circuit is increased. Further, equalization circuits precharge/equalize bit line potentials in a standby state of a dynamic random access memory. However, an equalization signal for driving the equalization circuits must also drive a large number of equalization circuits and hence has a large load capacitance. In addition, a wire transmitting the equalization signal is lengthened. According to the conventional structure, therefore, the operating speed is limited due to remarkable transmission delay of the equalization signal. Further, power consumption in a circuit generating the equalization signal is increased similarly to the case of the aforementioned BLI generation circuit.
In addition, the structures and operations of circuits for driving a memory cell array, including those for driving sense amplifiers and word lines, are not suitable for high-speed operations and low power consumption. Thus, such structures and operations must be improved.
Further, the circuits for driving the memory cell array include a number of circuits operated at a voltage (boost voltage) higher than a power supply voltage in general, leading to characteristic fluctuation of transistors in these circuits, i.e., a problem of reliability.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor device having low power consumption and high reliability, and capable of high-speed operations.
A semiconductor device according to an aspect of the present invention comprises a memory cell array including a plurality of memory cells arranged in the form of a matrix, a plurality of word lines arranged in correspondence to rows and a plurality of bit lines arranged in correspondence to columns, a sense amplifier circuit for reading data from or writing data in the memory cells, a selection gate for selectively coupling the memory cell array with the sense amplifier circuit, a transmission wire transmitting a control signal for on-off controlling the selection gate and a control signal driver arranged on an intermediate position of the transmission wire for driving the potential of the control signal.
Preferably, the semiconductor device further comprises a driver arranged on an end of the transmission wire for driving the potential of the control signal. Preferably, a plurality of such control signal drivers are provided, and the plurality of control signal drivers are dispersively arranged on the transmission wire.
In particular, the control signal driver pulls up or pulls down the potential of the control signal.
Preferably, the control signal driver drives the potential of the control signal in a direction changing the potential of the control signal in transition from a standby period to an active period for coupling the memory cell array with the sense amplifier circuit.
Preferably, the semico
Mitsubishi Denki & Kabushiki Kaisha
Tran M.
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