Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-11-12
2002-05-21
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C257S401000
Reexamination Certificate
active
06392279
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and a method for the production thereof and more particularly to a semiconductor device incorporating therein a MOS transistor and a method for the production thereof.
2. Description of the Prior Art
In recent years, the advance of the information industry has reached the point where the information processing needs further integration and further increase of speed. For the computers to fulfill this need, increases in capacity and in operating speed constitute themselves essential requirements. For the purpose of realizing in the computers these increases in capacity and operating speed, the computers are in need of such LSI's as are capable of high-speed operation and high integration and also such transistor elements as are extremely minute in size and highly prominent in quality.
For the sake of vesting the LSI's with high-speed operation and high integration, it is the most effective and explicit measure simply to miniaturize the component devices of the circuits. In the existent MOS transistors, the gates are on the verge of contracting to lengths of not more than 0.3 &mgr;m. The term “gate length” as used herein means the length of a gate electrode taken in the direction from the source to the drain thereof. This definition holds good in the following description. The length from the source to the drain along the gate length will be referred to herein below as “channel length.”
Incidentally, the formation of a gate electrode which determines this gate length is governed by the photolithography and the etching technique and the limit of the contraction of the gate length depends on the limits which are imposed on the resist exposure device, the etching device, and the like. Further, the accuracy required in positioning the gate electrodes for exposure and the allowance for the margin relative to the finishing width of the gate electrodes are other problems. In the circumstances, the promotion of stable quantity production of MOS transistors calls for maturity of the pertinent technique and the immediate start of the quantity production is difficult to attain.
As a means to decrease the gate length, JP-A-07-263,677 discloses a technique which comprises the steps of forming an oxide film pattern, growing a doped polysilicon film on the entire substrate, then allowing the doped polysilicon film to remain in a narrow width as a gate electrode on the lateral part of the oxide film, and subsequently removing the oxide film pattern. In this case, during the removal of the oxide film, the insulating film formed of the same substance as the oxide film and intended to separate the adjacent elements is simultaneously etched. The contraction of the element-separating insulating film, therefore, renders appropriate separation of the adjacent elements no longer feasible.
If the miniaturization of elements thus contemplated is realized, it will still entail other problems. In spite of the miniaturization of devices, the producers of such devices tend to adhere to the conventional standard value of 5 V as the power source voltage for the circuits in consideration of such factors as the generalization of elements and the ensurance of tolerable margin in the S/N ratio on the part of the users of the devices. This fact gives rise to the problem of requiring the devices to be enabled to operate in an exalted electric field. Now, this problem will be described below.
In the MOS transistor, when the gate length or the channel length is contracted without changing the power source voltage, the depletion layer which occurs in the neighborhood of the drain layer grows to reach the source layer and, consequently, lowers the diffusion potential of the source layer and degrades the junction pressure resistance between the source and the drain.
Further, when the drain field begins to manifest its influence in the channel area of the semiconductor layer directly below the gate electrode, the inversion threshold voltage in the channel area of the MOS transistor is no longer easily controlled with the gate voltage, and the threshold voltage (V
th
) of the gate voltage is lowered, and the subthreshold property concerning the device operation below the threshold voltage is deteriorated.
For the purpose of diminishing the depletion layer expanding in the semiconductor substrate under the gate electrode, a method which consists in heightening the concentration of an impurity in the semiconductor substrate directly below the gate electrode and a method which resides in decreasing the thickness of the gate oxide film have been adopted. These methods, however, entail other problems anew.
First, the increase of the concentration of an impurity in the semiconductor substrate results in sharpening the gradient of concentration between the drain diffusion layer and the semiconductor substrate, further expanding the drain field, affecting the drift speed of the migrating carrier itself, attenuating the mobility of the carrier, and lowering the drain current. Further, the energy of a high electric field applied between the drain diffusion layer and the substrate adds to the average energy of the migrating carrier and induces a hot carrier.
Then, the decrease of the thickness of the gate oxide film results in enlarging the effective gate field applied to the gate oxide film itself, exerting a heavy load on the insulation pressure resistance of the gate oxide film, and degrading the resistance of the hot carrier.
It has been heretofore customary to solve these problems by forming a gate electrode
101
of a MOS transistor through the medium of a gate insulating film
103
on a semiconductor substrate
102
, then forming a shallow layer
104
having an impurity diffused therein at a low concentration (hereinafter referred to as “low-concentration impurity diffused layer”), and thereafter forming insulating side walls
105
one each on the opposite sides of the gate electrode
101
as illustrated in FIG.
12
A and subsequently forming in the semiconductor substrate
102
a deep layer
106
having an impurity diffused at a high concentration while using the gate electrode
101
and the insulating side walls
105
as masks as illustrated in
FIG. 12B
, whereby the layers
104
and
106
having the impurity diffused at the low and the high concentration constitute themselves a source layer
107
and a drain layer
108
of the LDD (lightly doped drain) structure.
The drain layer
108
of the LDD structure described above diminishes the inclination of the concentration of an impurity in the part, approximating closely to the gate electrode
101
, alleviates the drain field concentrated locally in the proximity of the gate electrode
101
, and consequently improves the hot carrier resistance.
In the formation of the LDD structure in the drain layer
108
, however, since this formation generally passes the step of simultaneously forming the insulating side walls
105
one each on the opposite sides of the gate electrode
101
, this step inevitably imparts the layer
104
having an impurity diffused at a low concentration additionally to the terminal part of the source layer
107
.
The low-concentration impurity diffused layer
104
in the source layer
107
, therefore, forms a cause for increasing the parasitic capacity and parasitic resistance of the MOS transistor and inevitably degrades the quality of the transistor. In summary, in the conventional MOS transistor which adopts the LDD structure has not easily reconciled the repression of an increase in electric field and the improvement of the quality of transistor.
SUMMARY OF THE INVENTION
This invention has for an object thereof the provision of a semiconductor device possessed of a MOS transistor capable of lowering the parasitic capacity and parasitic resistance, promoting the addition to the speed of operation, and easily permitting miniaturization and a method for the production of a semiconductor device which represses the decrease in thickness of an insul
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Loke Steven
Vu Hung Kim
LandOfFree
Semiconductor device having LDD structure adapted to lower... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having LDD structure adapted to lower..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having LDD structure adapted to lower... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2830584