Semiconductor device having layers with varying lifetime charact

Active solid-state devices (e.g. – transistors – solid-state diode – Including region containing crystal damage

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257156, 257577, 257612, 257655, 257656, 257657, H01L 29207, H01L 29227, H01L 310288, H01L 31111

Patent

active

057172447

ABSTRACT:
An N.sup.- layer (11) of a low impurity concentration is formed on an upper major surface of an N.sup.+ layer (13) of a high impurity concentration in a diode (10). A P layer (12) is further formed on its upper major surface. The N.sup.- layer (11) is in a multilayer structure of first to third regions (11a to 11c) having carrier lifetimes .tau..sub.1, .tau..sub.2 and .tau..sub.3 respectively. These lifetimes are in relation .tau..sub.2 <.tau..sub.1 <.tau..sub.3. Due to the large lifetime .tau..sub.3 of the third region (11c), soft recovery can be implemented. The fact that the lifetime .tau..sub.3 of the third region (11c) is large serves as a factor reducing a forward voltage V.sub.f. It is possible to attain soft recovery without increasing the forward voltage V.sub.F by properly designing these lifetimes and thicknesses.

REFERENCES:
patent: 4259683 (1981-03-01), Adler et al.
patent: 4594602 (1986-06-01), Iimura et al.
patent: 4752818 (1988-06-01), Kushida et al.

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