Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-11-25
2001-10-23
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S077000, C257S129000, C257S488000
Reexamination Certificate
active
06307232
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a lateral high breakdown voltage element, and more specifically, to a semiconductor device having a lateral high breakdown voltage element with an SOI (Semiconductor on Insulator) structure and capable of maintaining a high breakdown voltage.
2. Description of the Background Art
First, a conventional technique will be described.
FIG. 36
is a schematic cross sectional view showing a first example of a conventional semiconductor device. With reference to
FIG. 36
, the semiconductor device is provided with an insulation substrate
103
. An n
−
semiconductor layer
102
(referred to as an SOI layer) is formed on insulation substrate
103
. An n
+
semiconductor region
104
with low resistance is formed in the surface of n
−
semiconductor layer
102
. A p
+
semiconductor region
105
is formed to surround the n
−
semiconductor layer
102
. A cathode electrode
106
is electrically connected to n
+
semiconductor region
104
. An anode electrode
107
is electrically connected to p
+
semiconductor region
105
. A back electrode
108
is formed on the back surface of insulation substrate
103
. An insulation film
109
is provided in n
−
semiconductor layer
102
for electrically isolating n
−
semiconductor layer
102
to provide a plurality of portions. An insulation layer
111
is provided on n
−
semiconductor layer
102
for electrically isolating cathode and anode electrodes
106
and
107
from other portions.
The operation of the semiconductor device will now be described.
With reference to
FIG. 37
, when anode and back electrodes
107
and
108
are at 0V and + voltage is applied to cathode electrode
106
, a depletion layer
133
extends from a pn junction between n
−
semiconductor layer
102
and p
+
semiconductor region
105
. The extension of depletion layer
133
stops when it reaches n
+
semiconductor region
104
. Depletion layer
133
is a kind of insulator, allowing no current flow between cathode and anode electrodes
106
and
107
. Such a semiconductor device is referred to as a diode.
Furthermore, addition of an insulation gate structure to this structure enables fabrication of a self-arc-extinguishing device such as an MOS (Metal Oxide Semiconductor) transistor, an IGBT (Insulated Gate Bipolar Transistor) or the like. It is noted that voltage is not allotted to insulation layer
103
in the above structure.
N
−
semiconductor layer
102
must be large to retain the major part of electric field in order to achieve higher breakdown voltage with a semiconductor device having the above structure. While horizontal (normal to the sheet of drawings) extension of the layer can be relatively readily achieved, vertical (longitudinal direction in the drawings) extension disadvantageously expands the isolation region as large thickness t
soi
of the SOI layer is required, making techniques for isolation and burying difficult.
FIG. 38
is a schematic cross sectional view showing a second example of a conventional semiconductor device. With reference to
FIG. 38
, n
−
semiconductor layer
102
is formed on a semiconductor substrate
101
with a buried insulation layer
103
formed of an oxide film interposed. Since other members in the drawing are almost the same as those for the conventional semiconductor device shown in
FIG. 36
, the same or corresponding portions have the same reference numerals and description thereof will not be repeated here.
The operation will now be described.
With reference to
FIG. 39
, when anode and back electrodes
107
and
108
are at 0V and + voltage is applied to cathode electrode
106
, a depletion layer A extends from a pn junction between n
−
semiconductor layer
102
and p
+
semiconductor region
105
. At the time, semiconductor substrate
101
is generally at 0V and functions as a field plate through buried insulation layer
103
, so that a depletion layer B extends from the interface between n
−
semiconductor layer
102
and buried insulation layer
103
toward the surface of n
−
semiconductor layer
102
in addition to the above mentioned depletion layer A. On the other hand, the electric field at the pn junction between n
−
semiconductor layer
102
and p
+
semiconductor region
105
is reduced as depletion layer B facilitates the extension of depletion layer A.
The effect is generally called RESURF (Reduced Surface Field) effect, and it is described in J. A. Appels et al., “HIGH VOLTAGE THIN LAYER DEVICES (RESURF DEVICES)”,
IEEE IEDM Tech. Dig.,
1979, pp. 238-241 that extending the pn junction along the interface rather than buried insulation layer
103
provides a similar effect.
In the above structure, a ratio of divided voltage per unit thickness of oxide film to silicon is that of a reciprocal of their dielectric constants (∈
oxi
=3.9, ∈
si
=11.7), that is, about 3:1. Thus, breakdown voltage can be increased by increasing the thickness of buried oxide film
3
retaining a considerable part of voltage.
This is shown FIG.
40
. RESURF effect is effective in the region where breakdown voltage increases with thickness. As the thickness of a film is simply increased, breakdown voltage (BV) reversely begins to decrease at a certain value. This is because the amount of extension for depletion layer B decreases as it is away from the ground voltage of semiconductor substrate
101
assisting the extension of depletion layer B, thereby undermining electric field reduction effect for depletion layer A. Accordingly, the thickness of the buried oxide film must be around 7 &mgr;m to achieve as high a breakdown voltage as 600V. In a film formation method, however, the formation of such a film with thickness of around 7 &mgr;m disadvantageously increases cost as considerably long processing time is required as shown in FIG.
41
.
A technique disclosed in Japanese patent Laying-Open No. 7-183522 will now be described as a conventional example for forming the thinnest possible buried oxide film while maintaining high breakdown voltage.
FIG. 42
is a schematic cross sectional view showing a structure of a semiconductor device disclosed in the aforementioned laid open application. With reference to
FIG. 42
, a semiconductor layer
102
is formed on a semiconductor substrate
101
with a buried insulation layer
103
interposed. A field oxide film layer
111
b
and an LDMOS transistor are formed in the surface of semiconductor layer
102
.
The LDMOS transistor includes a channel region
105
a
, a source region
105
b
, a drain region
104
, a drift region
120
, a gate oxide insulation layer
111
a
and a gate electrode layer
112
. Channel region
105
a
is formed on one side of field oxide film layer
111
b
, whereas source region
105
b
is positioned in the surface of channel region
105
a
. Drain region
104
is positioned in the surface on the side opposite to source region
105
b
with field oxide insulation layer
111
a
sandwiched.
Gate electrode layer
112
is formed on channel region
105
a
with gate oxide insulation layer
111
a
therebetween and extends over field oxide layer
111
b.
Drift region
120
is formed from the bottom surface of field oxide insulation layer
111
a
to that of semiconductor layer
102
and toward the side of drain region
104
from that of source region
105
b
, and formed of SiC (Silicon Carbide), for example.
In addition, a source electrode
107
and a drain electrode
106
are formed to be electrically connected to source and channel regions
105
b
and
105
a
as well as drain region
104
, respectively.
An SiC layer used for drift region
120
does not exert any influence specific to SiC in chemical treatment, photolithography and implantation diffusion steps for the surface of SOI layer, thereby allowing fabrication of a device directly using a standard Si process.
SiC has a wider band gap than Si (Silicon), the ma
Akiyama Hajime
Tarui Yoichiro
Hu Shouxiang
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Thomas Tom
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