Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-24
2004-04-06
Lee, Eddie (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S379000
Reexamination Certificate
active
06717209
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a fabricating method therefor, and more particularly to a semiconductor device having a junction diode and a fabricating method therefor wherein the junction diode is configured for preventing a gate insulating layer from deterioration arising from a plasma etch process necessary for device wire layout.
2. Description of the Prior Art
As ULSI semiconductor technology advances, there is an ever-increasing demand for high integration, fine wire and gate patterns, high performance, and wafers of large diameter and high yield. For this reason, the plasma process has become an indispensable technology in the field of semiconductor device fabrication.
Representative examples of plasma processes include the well-known processes of dry etching, thin layer deposition with plasma CVD, ashing, blanket etch-back and the like. As compared to the conventional wet-etching process, the dry-etching process offers the advantage of enabling ultra-fine pattern formation due to its anisotropic etching properties. For this reason, dry-etching has become widely used for highly integrated device fabrication.
FIG. 1
is a perspective view illustrating a conventional semiconductor device constructed under the aforementioned plasma process. For illustrative purposes, an NMOS transistor is described below.
In accordance with
FIG. 1
, the conventional semiconductor device includes: a field oxide layer
12
(for instance, P type) formed in a device isolating region on a semiconductor substrate
10
of a first conductivity type; a gate wire
16
positioned at a predetermined portion of an active region of the substrate
10
above a gate insulating layer
14
; a high-density source/drain region
18
of a second conductivity type (for instance, N+ type) formed in the active region at both edges of the gate wire
16
; an inter-level insulating layer
20
having contact holes (h) formed on the resultant structure of the prior processes to expose a predetermined portion of the surface of the gate wire
16
; conductivity plugs
22
(for instance, W plug) formed in the contact holes; and a metal wire
24
formed on the inter-level insulating layer
20
connected to the device terminals via the conductivity plug
22
.
FIG. 2
is an equivalent circuit diagram of the semiconductor device shown in FIG.
1
. As shown in the circuit, the device is constructed to enable the metal wire
24
to be electrically connected with the gate wire G of the NMOS transistor through the conductivity plug
22
.
Fabrication of the aforementioned structure results in numerous problems and limitations in the finished device, as specified below.
During an etching process (for example a dry etching process utilized to form an interconnect wire
24
, or an ashing process used to eliminate a photo resist layer pattern or the like) employing a plasma process, a large quantity of irregular charge (referred to as “plasma charge”) can form. As a result, during etching, a portion of the plasma charge can become infused along lateral walls of, or on the surface of, the metal layer of the wire
24
.
Accordingly, the plasma charge infused into the metal layer is collected and blocked by the gate insulating layer
14
, which often times becomes a major cause of a damage to the gate insulating layer
14
, referred to in the art as “plasma damage”. In other words, the plasma damage is imparted on the gate insulating layer because the device is constructed to migrate the plasma charge generated during the course of the plasma etching process through the conductivity plug
22
and the gate wire
16
toward the gate insulating layer
14
.
In the case of plasma damage, the accumulated charge, and the resulting impurities in the gate insulating layer
14
, cause a reduction in performance of the semiconductor device. However, in the case of a severe defect, for example if the deterioration is so profound so as to reduce the thickness of the gate insulating layer
14
to less than 100 angstroms, a total breakdown of the gate insulating layer
14
is likely, which further reduces the reliability of the semiconductor device.
In addition to immediate damage, which often times can be screened at an early stage, a large number of plasma-damage-related defects are detectable only at relatively later stages during device lifetime, for example when the semiconductor device is deployed and used by consumers. For this reason, there is a need to address and resolve the aforementioned limitations.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor device having a junction diode (for example a unidirectional or bi-directional junction diode), in the process of forming a wire in the device. The junction diode serves as a pathway for excessive plasma charge, generated during the plasma etching process of wire formation, to be discharged through the semiconductor substrate.
The semiconductor device includes a junction diode (a unidirectional or bi-directional junction diode) formed in the substrate at a predetermined distance apart from a gate wire of a transistor. The gate wire is coupled through an insulating layer to a metal wire, and the diode(s) are coupled to a dummy metal pattern formed proximal to the metal wire. In this manner, plasma charge generated during wire formation, is discharged into the semiconductor substrate through the junction diode, preventing accumulation of the plasma charge in the gate insulating layer of the device. Deterioration of the gate insulating layer is thereby avoided.
It is another object of the present invention to provide a method for fabricating the semiconductor device constructed as described above.
In order to accomplish the aforementioned object of the present invention, there is provided a semiconductor device having a junction diode in a first embodiment of the present invention comprising: a first conductivity-type semiconductor substrate; a gate wire formed over a gate insulating layer on a predetermined portion of the substrate; second conductivity-type source/drain regions formed in the substrate at opposite edges of gate wire; a second conductivity-type junction diode formed in the substrate at a predetermined distance apart from the source/drain regions; an inter-level insulating layer formed over the gate wire, the source/drain regions and the junction diode; first and second contact holes penetrating through the inter-level insulating layer to expose predetermined portions of the gate wire and junction diode; first and second conductivity plugs formed in the respective first and second contact holes; a metal wire formed on a predetermined portion of the inter-level insulating layer coupled with the gate wire through the first conductivity plug; and a dummy metal pattern formed on the inter-level insulating layer at a predetermined distance apart from the metal wire coupled with the junction diode through the second conductivity plug.
The dummy metal pattern may be configured in a linear stripe or double folded shape. It is preferable that the dummy metal pattern is shorter than the metal wire in total length. Furthermore, the dummy metal pattern and the metal wire may comprise the same material, and a gap width W between the metal wire and the dummy metal pattern is preferably formed at less than 2 micro-meter (&mgr;m), the width W representing the minimum horizontal distance between the metal wire and the dummy metal pattern.
In order to accomplish the aforementioned object of present invention, there is additionally provided a semiconductor device having a junction diode in a second embodiment of the present invention comprising: a semiconductor substrate including first and second conductivity-type wells; a gate wire formed over a gate Insulating layer on a predetermined portion of the first conductivity-type well; source/drain regions formed in the first conductivity-type well at opposite edges of gate wire; a second conductivity-type first juncti
Kang Hee-Sung
Kim Young-Kwang
Lee Eddie
Mills & Onello LLP
Owens Douglas W.
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