Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-10-30
2004-04-13
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S351000, C257S370000, C257S371000, C257S456000, C257S384000
Reexamination Certificate
active
06720627
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and a fabrication method thereof, and more particularly to a method for forming a titanium silicide film which is low in electric resist layerance and excellent in heat resist layerance, and a semiconductor device, such as a salicide CMOS transistor, which is reduced in junction leakage currents and suppressed in short-channel effect for raising drive power, and a method of fabricating the same.
2. Related Art
In insulated-gate field effect transistors employed in semiconductor integrated circuits currently available, there is reduction of depletion-layer electric charges carried by a gate electrode relative to the total amount of depletion-layer electric charges, as the device miniaturizes. As a result, the transistor is apt to cause short-channel effects involving lowering of threshold voltage, punch-through, and degradation in sub-threshold characteristics. One factor of such phenomenon is attributable to deep junctions of source and drain regions.
To suppress the short-channel effect, there arises a necessity of making junctions of source and drain regions shallower in commensurate with miniaturization of the device. In PMOS semiconductor devices, there is a general tendency of adopting a surface-channel transistor provided with p-type doping, because the conventional buried-channel transistor with an n-doped gate electrode cannot cope with steping of fine linewidth. With such structure, the gate electrode is built in a dual-gate type. To simplify fabrication steps, the gate electrode is subjected to doping simultaneous with formation of source and drain regions respectively for NMOS and PMOS structures. A self-aligned silicide technique (a salicide technique) also comes to broad utilization for raising drive power of the transistor, accompanied by finer steping and shallower junctions.
A device fabrication method, e.g., shown in FIGS.
26
(
a
)-
26
(
e
), is conventionally known as a self-aligned silicide technique (a salicide-transistor technique) (K. Tsukamoto, T. Okamoto, M. Shimizu, T. Matsukawa and H. Harada: Extended Abstracts 16th Int. Conf. Solid State Devices & Materials, Kobe 1984 (Business Center for Academics Societies Japan, Tokyo, 1984) see p. 47). The method of FIGS.
26
(
a
)-
26
(
e
) will be explained hereinbelow.
Referring to FIG.
26
(
a
), a silicon semiconductor substrate
601
is formed thereon a field oxide layer
602
, a gate oxide film
603
, and a gate electrode of polysilicon
604
having side walls thereof covered with an insulation film. The gate electrode contains phosphorus as impurity ions diffused into polysilicon prior to patterning thereof. Then, as shown in FIG.
26
(
b
), an oxide film
606
is deposited and a high concentration of impurity ions are implanted into areas for source and drain through the oxide film
606
with using photo-resist layer as a mask, not shown. As for impurity ions, arsenic ions are employed for an n-channel, while boron is used for a p-channel. Thereafter, a heat treatment for activation is performed, e.g., in a nitrogen ambient at 900° C. for 30 minutes for formation of source and drain regions
607
. The oxide film
606
is then removed from the surface of the source and rain regions
607
and the gate electrode
604
, and thereafter a titanium film
608
is deposited by sputtering in an argon ambient, as shown in FIG.
26
(
c
). Then, a first rapid thermal anneal is performed in a nitrogen ambient at 675° C. for approximately 20 seconds, as shown in FIG.
26
(
d
) to react titanium with silicon in the surface layers of the source and drain regions
607
and the gate electrode
604
, thereby forming a titanium silicide (TiSi
2
) of a C49-crystal structure which is stoichiometrically metas-table. On this occasion, the surface of the titanium film
608
alters to a titanium nitride film
609
. Etching is then made with using a solution mixture of sulfuric acid and hydrogen peroxide to remove unreacted titanium
608
and a titanium nitride film
609
formed by the first rapid thermal anneal, as shown in FIG.
26
(
e
). Thereafter, a second rapid thermal anneal is performed in an nitrogen ambient at 800° C. for approximately 20 seconds to transform the titanium silicide film
610
into a titanium silicide film (TiSi
2
) of a C54-crystal structure which is stoichiometrically stable.
There is also illustrated in FIGS.
28
(
a
)-
28
(
c
) and FIGS.
29
(
d
)-
29
(
g
) a conventional fabrication step utilizing a salicide technique for a dual-gate CMOS device. The step is briefly explained with reference to the drawings.
Referring to FIG.
28
(
a
), a silicon semiconductor substrate
801
is first formed with a p-well
802
and an isolation layer
803
. Thereafter, a gate dielectric film
804
is formed on the substrate, and a gate electrode
805
is formed to a thickness of, i.e., 2500 angstroms. Then, a thin insulation film
806
is deposited to implant
31
p
+
ions, thereby forming low-concentration (LDD) region
807
, as shown in FIG.
28
(
b
), followed by deposition of a thick insulation film
808
to a thickness of, e.g., 1000 angstroms, as shown in FIG.
28
(
c
) . The thick insulation film is then subjected to isotropic etching to form side wall spacers
809
on side walls of the gate electrode
805
, as shown in FIG.
29
(
d
). Subsequently, a thin insulation film
810
is deposited and then
75
AS
+
ions are implanted in a higher concentration, e.g., 3×10
15
/cm
2
, than the
31
p
+
ions with an implant energy of 40 keV, for forming source and drain regions
811
and n
+
-doping the gate electrode
805
, as shown in FIG.
29
(
e
). Then, annealing is done in a nitrogen ambient at 850° C. for 10 minutes and treated by furnace annealing or RTA (Rapid thermal anneal) at 1000° C. for 20 seconds, for activating n
+
ions and restoring crystal defects in the LDD regions
808
, the source and drain regions
811
, and the gate electrode
805
, as shown in FIG.
29
(
g
). A refractory metal is then deposited by a technique such as sputtering and forming salicide
812
in a self-aligned manner through a heat treatment such as two-step RTA, providing a semiconductor device.
However, the conventional titanium silicide film forming step as above involves problems as given below.
(1) In a reaction system of Ti and Si, impurity ions are implanted through an oxide film, so that oxygen atoms, i.e., oxygen atoms undergoing knock-on upon implant of impurity ions, are inevitably mixed into a silicon semiconductor substrate (See FIG.
27
). The mixing of oxygen atoms is particularly prominent when implanting heavy ions, resulting in silicidation reaction in a ternary elenent system of Ti, Si, and O.
(2) Silicidation by the ternary elenent system does not proceed necessary silicidation. Further, SiO
2
is preferentially formed in grain boundaries of TiSi
2
, raising the sheet resist layerance and worsening the heat resist layerance of the titanium silicide film.
(3) Particularly, where silicidation is made in a linewidth finer than the grain size of TiSi
2
, the above problem (2) is prominent. That is, in silicidation in a linewidth finer than the grain size of TiSi
2
, transformation C49 into a C54-crystal structure from C49 is inapt to occur by a rapid thermal annealing (an RTA treatment) at 900° C. or below, giving a high-resist layerance titanium silicide film. Conversely, where the RTA treatment is performed at a high temperature of 900° C. or higher, the transformation of from C49 into the C54-crystal structure is apt to occur. However, there arises worsening of heat resist layerance and causing aggregation of TiSi
2
as compared with a broader linewidth of titanium silicide films. Further, with a treatment at such temperature, aggregation begins to occur due to the effect of oxygen atoms even for titanium silicide films with a broader linewidth. There is therefore a problem that aggregation is certain to occur in a finer linewidth of titanium silicide films.
(4) In conventional silic
Hayashida Shigeki
Iwata Hiroshi
Kakimoto Seizou
Matsuoka Toshimasa
Nakano Masayuki
Flynn Nathan J.
Sefer Ahmed N.
Sharp Kabushiki Kaisha
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