Semiconductor device having interconnection layer contacting sou

Details Semiconductor device having interconnection layer contacting sou Semiconductor device having interconnection layer contacting sou

1991-04-26

1992-12-22

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257900, 257408, H01L 2968, H01L 2906, H01L 2934

Patent

active

051737523

ABSTRACT:
A semiconductor device incloudes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.

REFERENCES:
patent: 4949136 (1990-08-01), Jain
patent: 5006481 (1991-04-01), Chan et al.
patent: 5023683 (1991-06-01), Yamada
"Novel Stacked Capacitor Cell for 64Mb DRAM", Wakamiya, et al., VLSI Technology Symposium, 1989, pp. 69-70.

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