Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2000-10-13
2003-02-25
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S684000, C257S730000, C438S110000, C438S123000
Reexamination Certificate
active
06525406
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor packages and, more particularly but not by way of limitation, to an improved method of manufacturing semiconductor packages having longer moisture-permeation paths, restoration of original coloring, improved silver-plating of leads in the package, improved solder joint force, and improved marking.
2. History of Related Art
It is conventional in the electronics industry to encapsulate one or more semiconductor devices, such as integrated circuit chips, in a semiconductor package. These plastic packages protect a chip from environmental hazards, and provide a method for electrically and mechanically attaching the chip to an intended device. Recently, such semiconductor packages have included metal leadframes for supporting an integrated circuit die which is bonded to a chip paddle region thereof. Bond wires which electrically connect pads on the integrated circuit die to individual leads of the leadframe are then incorporated. A hard plastic encapsulant material which covers the bond wire, the integrated circuit die and other components, forms the exterior of the package. A primary focus in this design is to provide the die with adequate protection from the external environment in a reliable and effective manner.
As set forth above, the semiconductor package herein described incorporates a leadframe as the central supporting structure of such a package. A portion of the leadframe completely surrounded by the plastic encapsulant is internal to the package. Portions of the leadframe extend internally from the package and are used to connect the package externally. More information relative to leadframe technology may be found in Chapter 8 of the book
Micro Electronics Packaging Handbook,
(1989), edited by R. Tummula and E. Rymaszewski which is incorporated herein by reference. This book is published by Van Nostrand Reinhold, 115 Fifth Avenue, New York, N.Y.
Once the integrated circuit dies or chips have been produced and encapsulated in a semiconductor package as described above, they may be used in a variety of electronic appliances. A wide variety of electronic devices have been developed in recent years, such as cellular phones, portable computers, etc. Each of these devices typically include a motherboard on which a significant number of such semiconductor packages are utilized to provide multiple electronic functions. These electronic appliances are themselves required to be reduced in size as consumer demand increases. Accordingly, not only are semiconductor chips highly integrated, but also semiconductor packages are miniaturized with a high increase of package mounting density.
According to such miniaturization tendency, semiconductor packages, which transmit electrical signals from semiconductor chips to motherboards and support the semiconductor chips on the motherboards, have been designed to have a size of about 1×1 mm to 10×10 mm. Examples of such semiconductor packages are referred to as MLF (micro leadframe) type semiconductor packages and MLP (micro leadframe package) type semiconductor packages. Both MLF type semiconductor packages and MLP type semiconductor packages are manufactured in the same manner. A description of several problems in the semiconductor package industry are described below.
During the manufacturing for a semiconductor package, electrical testing is required to insure proper function of the semiconductor package. This testing occurs after the semiconductor package has been separated from a matrix of semiconductor packages by singulation. Because of this limitation, a multitude of semiconductor packages must be individually tested. The time required to individually test these packages, in addition to the small size of the packages, results in decreased efficiency and higher costs.
Due to the large number of leads present in modern miniaturized semiconductor packages, it is desirable to locate a recognition mark on the semiconductor package to identify the first lead. In prior art semiconductor packages, the recognition mark is difficult to form on the package body due to the narrow region formed at the top surface of the encapsulant after the package has been formed. In addition, the position of the mark in the semiconductor package area reduces the marking area for characters, symbols and/or logos. Further, when the recognition mark is deep, the conductive wires are disadvantageously exposed due to the thinness of the packaged body.
During a typical singulation process in the manufacturing of the packaged semiconductor, a burr is formed at the end of the internal lead directed downwardly along the cut or external side of the internal lead. This burr reduces the contact area between the internal lead and the motherboard during mounting which adversely affects the solder joint force. In addition, due to the presence of the burr, solder used to affix the packaged semiconductor to the motherboard cannot sufficiently ascend along the wall of the end of the internal lead, so that the solder joint force of the internal lead is further reduced.
Typical semiconductor packages have a silver plated layer in such a design that the layer is positioned inside the package body. Such a conventional leadframe or semiconductor package suffers from a significant problem in that it is very difficult to conform to the tolerances required regarding the application of the silver plated layer. When the silver plated layer is positioned inside the packaged body, the plated layer must be confined within a relatively small space, which requires that the plating technique be very precise. The increased precision requirement often leads to defective semiconductor packages.
A further problem of a conventional semiconductor package is that a typical chip paddle or die pad has a half-etched section of the chip paddle that is formed only at a lower edge area of the chip paddle along the chip paddle perimeter. The size or length of the half-etched section is insufficient to thoroughly prevent moisture from permeating into the vicinity of the semiconductor chip. Thus, much moisture may be collected in the vicinity of the semiconductor chip under the high temperature conditions that exist during the operation of a semiconductor chip. The moisture may then spread widely over the inside of the semiconductor package, resulting in cracking of the semiconductor package or causing protuberances to form on the surface of the semiconductor package.
Finally, in a typical process to deflash a semiconductor, the leadframes may turn a yellowish color. A discolored semiconductor package, even though not dysfunctional, may have a reduced commercial value. In addition, a fatal problem may occur when the leadframe packages are subjected to electronic sensing. The leadframe may be so discolored that electrical sensing apparatuses cannot accurately detect the internal leads because of a decrease in the light reflected from the discolored internal leads. This problem is most prevalent when testing the semiconductor packages or mounting the packages onto motherboards. The result may be a large number of defects that can occur during the subsequent mounting process.
BRIEF SUMMARY OF THE INVENTION
In the various embodiments of the present invention, there is disclosed a semiconductor package and a method for manufacturing the same. First, a leadframe is provided. A planar or substantially planar die pad is within the leadframe and is connected to the leadframe by a plurality of tie bars. The die pad is half-etched on a perimeter of the upper and lower surface to increase the moisture-permeation path of the finished package. A plurality of finger-like rectangular leads extend from the leadframe towards the die pad without contacting the die pad. A silver plating layer is formed on the upper surface of the leadframe. A semiconductor chip having a plurality of bond pads is mounted on the upper surface of the die pad or chip paddle in the leadframe. Dam bars are pr
Chung Young Suk
Hong Ku Sun
Jang Sung Sik
Lee Hyung Ju
Lee Jae Jin
Amkor Technology Inc.
Le Dung Anh
Nelms David
Stentina Brunda Garred & Brucker
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