Semiconductor device having improved power density

Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – With electric field controlling semiconductor layer having a...

Reexamination Certificate

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C257S341000

Reexamination Certificate

active

10999704

ABSTRACT:
An MOS device is formed including a semiconductor layer of a first conductivity type, and source and drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The source and drain regions are spaced apart relative to one another. A drift region of the second conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the source and drain regions, the drift region having an impurity doping concentration greater than about 2.0e12 atoms/cm2. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer. The device further includes a gate formed on the insulating layer at least partially between the source and drain regions, and a buried layer of the first conductivity type formed in the semiconductor layer in close relative proximity to and beneath at least a portion of the drift region. A substantially vertical distance between the buried layer and the drift region, and/or one or more physical dimensions of the buried layer are configured so as to optimize a power density of the device relative to at least one of an on-resistance and a maximum drain current of the device.

REFERENCES:
patent: 5086332 (1992-02-01), Nakagawa et al.
patent: 6608351 (2003-08-01), Meeuwsen et al.
patent: 2002/0185679 (2002-12-01), Baliga
patent: 2003/0228737 (2003-12-01), Efland et al.
patent: 10311699 (2004-11-01), None
Translation of Taddiken DE 10311699.
S. Xu et al., “High Power Silicon RF LDMOSFET Technology for 2.1GHz Power Amplifier Applications,” Proceedings ISPSD 2003, Apr. 14-17, 2003, pp. 190-193.
A. Ludikhuize, “A Review of RESURF Technology,” Proceedings of IEEE ISPSD 2000, May 22-25, 2000, France, pp. 11-18.
M. Amato et al., “Comparison of Lateral and Vertical DMOS Specific On-Resistance,” Proceedings of IEEE IEDM 1985, pp. 736-739.
E.H. Stupp et al., “Low Specific On-Resistance 400V LDMOST,” Proceedings of IEEE IEDM 1981, pp. 426-428.
J. Olsson et al., “1 W/mm RF Power Density at 3.2 GHz for a Dual-Layer RESURF LDMOS Transistor,” IEEE Electron Device Letters, vol. 23, No. 4, Apr. 2002, pp. 206-208.
H. Brech et al., “Voltage Optimization for State of the Art RF-LDMOS for 2.1 GHz W-CDMA Cellular Infrastructure Applications,” Proceedings of IEEE MTT-S Digest 2003, pp. 209-212.
M. Shindo et al., “High Power LDMOS for Cellular Base Station Applications,” Proceedings of IEEE ISPSD 2001, pp. 107-110.
S. Manzini et al., “Hot-Electron-Induced Degradation in High-Voltage Submicron DMOS Transistors,” Proc. IEEE ISPSD, 1996, pp. 65-68.

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