Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2001-06-11
2002-05-07
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C257S531000, C336S200000, C438S329000, C438S381000, C438S422000
Reexamination Certificate
active
06383889
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an integration of passive devices or passive and active devices on a single semiconductor substrate, wherein the passive device has at least a conductive layer having a reduced parasitic capacitance to the substrate and also relates to improvements for the semiconductor device to have high resistance to pressure and vibration.
The recent years, it has been proposed that in addition to active devices such as MOS field effect transistors and bipolar transistors, passive devices such as inductors and capacitors be integrated on the same LSI chip. The formation of the passive device on the silicon substrate may raise the problem in deterioration of electric characteristics of the passive devices due to a parasitic capacitance between the silicon substrate and conductive layer in the passive device. In Japanese laid-open patent publication No. 7-122710, it is disclosed to form a deep cavity in the silicon substrate under the passive device formation region on which the passive device will be formed. In Symposium on VLSI Technology Digest of Technical Papers, 1996 D. Hisamoto et al., it is addressed that an inductor device as the passive device is integrated on the silicon substrate. This conventional technique will be described in detail with reference to
FIGS. 1
,
2
and
3
.
FIG. 1
is a fragmentary cross sectional elevational view illustrative of a conventional semiconductor device having an inductive device as a passive device on a silicon substrate.
FIG. 2
is a cross sectional plan view illustrative of a silicon substrate on which an inductive device as a passive device is integrated to form the conventional semiconductor device of
FIG. 1
which is a cross sectional elevation view taken along I-I′ line of FIG.
2
.
FIG. 3
is a plan view illustrative of the conventional semiconductor device of
FIG. 1
, which is a cross sectional elevation view taken along a I-I′ line of FIG.
3
.
A cavity
72
is formed in a silicon substrate
61
. A silicon oxide film
65
is formed on a surface of the silicon substrate so that the bottom of the silicon oxide film
65
defines an upper boundary of the cavity
72
. An inter-layer insulator
67
is formed on the silicon oxide layer
65
. A first level interconnection
66
is formed on the silicon oxide film
65
and within the inter-layer insulator
67
. A contact plug
68
is formed on the first level interconnection
66
and within the inter-layer insulator
67
. Second level interconnections
70
are formed on the inter-layer insulator
67
. A through hole
71
is formed which penetrate both the inter-layer insulator
67
and the silicon oxide layer
65
so that the through hole
71
reaches the cavity
72
formed in the silicon substrate
61
. An inductor device
76
comprising the first and second level interconnections
66
and
70
is thus formed over the cavity
72
formed in the silicon substrate
61
. Namely, the cavity
72
extends under the entire of the inductor device formation region on which the inductor device
76
is formed. The cavity
72
reduces the parasitic capacitance between the silicon substrate
61
and the first and second level interconnections
66
and
70
, thereby improving frequency characteristics of the inductor device
76
. Namely, the high frequency performance of the inductor device is improved by the cavity
72
. The inductor device has an inductance in the range of 7.6-7.7 nH and also improves the resonant frequency from 8.7 GHz to 19.6 GHz, namely the resonant frequency is increased by two times or more.
The inductance “L” of the inductor device depends upon the external dimension “X” and the number of windings “n” as well as a width “W” of the interconnections and a pitch “S” of the interconnections.
FIG. 4
is a diagram illustrative of the dependency of an inductance “L” upon the external dimension “X” of the inductor device, where the width “W” and the pitch “S” of the interconnections are 20 micrometers and the number of windings “n” is 3.5.
In order to obtain the inductance in the range of 7.6-7.7 nH, it is necessary that the external dimension “X” of the inductor device be 500 micrometers and that the cavity size be 500 micrometers by 500 micormeters. If vibration and pressure are applied to the semiconductor device, the silicon oxide film
65
and the inter-layer insulator
67
may be broken, whereby the inductor device
76
is dropped into the cavity
72
formed in the silicon substrate
61
.
In the above circumstances, it was required to develop a novel semiconductor device having an integration of passive devices or passive and active devices on a single semiconductor substrate, wherein the passive device has at least a conductive layer having a reduced parasitic capacitance to the substrate and also the semiconductor device is improved in mechanical strength against external mechanical forces such as pressure and vibration.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel semiconductor device having an integration of passive devices or passive and active devices on a single semiconductor substrate free from the above problems.
It is a further object of the present invention to provide a novel semiconductor device having an integration of passive devices or passive and active devices on a single semiconductor substrate, wherein characteristics and performance of the passive device are improved.
It is a still further object of the present invention to provide a novel semiconductor device having an integration of passive devices or passive and active devices on a single semiconductor substrate, wherein high frequency performance of the inductor device is improved.
It is yet a further object of the present invention to provide a novel semiconductor device having an integration of passive devices or passive and active devices on a single semiconductor substrate, wherein mechanical strength of the semiconductor device against external forces such as pressure and vibration are improved.
It is a further object of the present invention to provide a novel method of forming a semiconductor device having an integration of passive devices or passive and active devices on a single semiconductor substrate free from the above problems.
It is still another object of the present invention to provide a novel method of forming a semiconductor device having an integration of passive devices or passive and active devices on a single semiconductor substrate, wherein characteristics and performance of the passive devices are improved.
It is moreover an object of the present invention to provide a novel method of forming a semiconductor device having an integration of passive devices or passive and active devices on a single semiconductor substrate, wherein high frequency performance of an inductor device is improved.
It is another object of the present invention to provide a novel method of forming a semiconductor device having an integration of passive devices or passive and active devices on a single semiconductor substrate, wherein mechanical strength of the semiconductor device against external forces such as pressure and vibration is improved.
The present invention provides a cavity structure formed in a semiconductor substrate and under a passive device formation region on which a passive device if formed, wherein the cavity structure has at least one of supporting pillars and supporting walls for providing the passive device formation region with a mechanical strength.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.
REFERENCES:
patent: 5567982 (1996-10-01), Bartelink
patent: 5863832 (1999-01-01), Doyle et al.
patent: 6057202 (2000-05-01), Chen et al.
patent: 6093599 (2000-07-01), Lee et al.
patent: 6197655 (2001-03-01), Montanini et al.
patent: 6221727 (2001-04-01), Chan et al.
patent: 6274920 (2001-08-01), Park et al.
pat
Duy Mai Anh
NEC Corporation
Young & Thompson
LandOfFree
Semiconductor device having improved parasitic capacitance... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having improved parasitic capacitance..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having improved parasitic capacitance... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2857545