Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-21
2001-09-18
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S411000
Reexamination Certificate
active
06291865
ABSTRACT:
This application claims the benefit of Korean Application No. 97-75403 filed Dec. 27, 1997, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method for fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving characteristic of the device.
2. Discussion of the Related Art
A background art semiconductor device will be described with reference to the accompanying drawings.
FIG. 1A
is a cross-sectional view illustrating a semiconductor device according to the background art.
FIG. 1B
is a cross-sectional view illustrating a pre-amorphijation (P-A) processed semiconductor device to have a small junction depth according to the background art.
FIG. 1C
is a cross-sectional view illustrating a semiconductor device having a Halo structure according to the background art.
Generally, a field effect transistor (FET) has a gate electrode formed on a gate insulator having the same dielectric constant in the overall region. As shown in
FIG. 1
, the FET according to background art includes a semiconductor substrate
1
, a gate insulator
2
, a gate electrode material layer
3
, and source/drain regions
4
a
and
4
b
. The gate insulator
2
constituting one material layer which has a particular dielectric constant is formed on the semiconductor substrate
1
. The gate electrode material layer
3
is formed on the gate insulator
3
. The source/drain regions
4
a
and
4
b
are formed in a surface of the semiconductor substrate
1
at both sides of the gate electrode material layer
3
.
In such a FET, a device is formed using the gate insulator
2
having a particular dielectric constant, and a channel inversion region is formed below the gate insulator
2
when a voltage is applied to the gate electrode, thereby moving carriers between the source/drain regions
4
a
and
4
b.
Electrical characteristic of the FET can be defined as follows.
Id
(
sat
)∝
Cox
=(&egr;
i.S
)/
Tox,
where, Id(sat) is a drain saturation current, Cox is a gate capacitance, &egr;i is a dielectric constant of the gate insulator, Tox is a gate thickness, and S is a cross-sectional area. Here, the dielectric constant of the gate insulator is obtained by multiplying a free space dielectric constant by a semiconductor specific inductive capacity.
A variable value of a threshold voltage is expressed as &Dgr;V
T
=(V
T S.C
−V
T L.C
)∝1/Cox=(Tox×S)/&egr;i, where V
T S.C
is a threshold voltage of a short channel, V
T L.C
is a threshold voltage of a long channel, and ∝1/Cox is a serve threshold value factor.
To prevent damage of the device due to a short channel effect and a punchthrough in the above-described FET, semiconductor devices shown in
FIGS. 1B and 1C
have been suggested.
In
FIG. 1B
, P-A process is performed to realize a small junction depth in the surface of the semiconductor substrate
1
where the source/drain regions
4
a
and
4
b
will be formed. An ion-implantation process is formed thereafter, so that the device is formed to have the gate insulator
2
having one level of dielectric constant.
If a voltage is applied to the gate electrode material layer
3
, an inversion layer is formed in a channel region below the gate insulator
2
, thereby flowing a current between the source/drain regions
4
a
and
4
b.
Before forming the source/drain regions
4
a
and
4
b
, the P-A process is performed to avoid an ion channeling. Therefore, the source/drain regions
4
a
and
4
b
are formed to have a small junction depth, thereby reducing a punchthrough.
In
FIG. 1C
, the FET having a Halo structure is demonstrated to eliminate a punchthrough. A short channel effect, which is undesirable to the device, occurs frequently as a channel length of a semiconductor device becomes shorter, especially in a metal oxide semiconductor field effect transistor (MOSFET). To solve such a problem, among various methods, there is a method for reducing a short channel effect by varying doping profile in a channel region using a Halo doping.
To form a Halo structure, a gate electrode material layer
3
is formed on the gate insulator
2
and impurity ions opposite to the source/drain regions are implanted into the semiconductor substrate at an angle of 0-45°. Alternatively, a gate sidewall spacer is formed and then impurity ions are tilted-implanted into the semiconductor substrate at an angle of 0-45°. In this process, B or BF
2
is used as the impurity ions for an n-MOS transistor.
In a transistor having such a Halo structure, a depletion region due to a drain bias is prevented from being expanded since a drain region is surrounded by a heavily doped region of a conductivity type opposite to the drain region. Thus, a punchthrough can be prevented from occurring in the short channel and drain induced barrier lowering (DIBL) can be reduced. Nonetheless, the aforementioned FET has several problems as follows.
In the background art FET, it is difficult to improve an on-off current characteristic and to reduce a short channel effect at the same time. Although the short channel effect can be reduced in the background art FET, there still remains a problem that a current is reduced as a resistance of source/drain increases.
Further, since a heavily doped region surrounds the source/drain region, a junction capacitance increases, thereby deteriorating characteristics of the device.
For the transistor of Halo structure, since a threshold voltage is varied depending on tilt-ion implantation, it is difficult to ensure a uniformity of the threshold voltage.
In particular, in reducing a thickness of the gate insulator to reduce a short channel effect, a gate breakdown, grid, and impurity scattering are caused, which deteriorate a current characteristic.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor device and a method of fabricating the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a semiconductor device and a method of fabricating the same, in which gate insulators of material regions having different dielectric constants are formed and a gate is formed on the gate insulators to improve characteristics of the device.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a semiconductor device includes a semiconductor substrate including a channel region, gate insulators of material layers having different dielectric constants on the channel region divided in longitudinal direction, a gate electrode formed on the gate insulating layers, and source/drain regions formed in a surface of the semiconductor substrate at both sides of the gate electrode.
In another aspect, a method for fabricating a semiconductor device according to the present invention includes the steps of forming a first gate insulator having a first dielectric constant &egr;1 on a semiconductor substrate, patterning the first gate insulator to remain in a source region on a channel region, forming a second gate insulator having a second dielectric constant &egr;2 on an exposed surface of the semiconductor substrate in a drain region on the channel region, depositing a material layer for gate electrode on the semiconductor substrate in which the first and second gate insulators are formed, forming a gate electrode layer by patterning the material la
LG Semicon Co. Ltd.
Morgan & Lewis & Bockius, LLP
Munson Gene M.
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