Semiconductor device having improved multilayered wirings

Details Semiconductor device having improved multilayered wirings Semiconductor device having improved multilayered wirings

1988-08-30

1990-05-08

Hille, Rolf

357 71, 357 45, H01L 2348, H01L 2946, H01L 2710

Patent

active

049242903

ABSTRACT:
A semiconductor device includes a circuit block formed on a semiconductor chip with multilayered wiring layers having two or more layers, and having a specific function assigned thereto, a first current path pattern formed in a first layer of the multilayered wiring layers and running around the circuit block, a second current path pattern formed in a second layer of the multilayered wiring layers and running around the circuit block, part of the second current path pattern lying over the first current path pattern and the other portion of the second current path pattern lying off the first current path pattern so as to define a connection space with a predetermined width between the first current path pattern and the second current path pattern, a first signal path pattern formed in the first layer of the multilayered wiring layers and serving as a signal path to the circuit block, a second signal path pattern formed in the second layer of the multilayered wiring layers and serving as the signal path to the circuit block, and a via contact, formed in the connection space, for electrically coupling the first signal path pattern and the second signal path pattern.

REFERENCES:
patent: 4453176 (1984-06-01), Chance et al.
patent: 4568961 (1986-02-01), Noto
patent: 4656370 (1987-04-01), Kanuma
patent: 4694320 (1987-09-01), Asano
patent: 4716452 (1987-12-01), Kondoh et al.
patent: 4811073 (1989-03-01), Kitamura et al.
Review of The Electrical Communication Laboratories, vol. 26, No. 9/10, Sep./Oct. 1978, pp. 1355-1366; K. Wada et al: "Master-Slice Layout Design for Emitter Coupled Logic LSI".
Proceedings of the First International IEEE VLSI Multilevel Interconnection Conference, New Orleans, LA, 21-22 Jun. 1984, pp. 290-297, IEEE; A. Feller et al: "A 1.24 micron CMOS-SOS DLM Optimized Standard Cell Technology".

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