Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – With electric field controlling semiconductor layer having a...
Reexamination Certificate
2000-03-09
2002-08-06
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
With means to increase breakdown voltage threshold
With electric field controlling semiconductor layer having a...
C257S492000, C257S144000, C257S152000, C257S487000
Reexamination Certificate
active
06429501
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No.
11-064591,
filed Mar. 11, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a high power semiconductor device and a method for manufacturing the device, and more particularly to an improvement in the structure of a junction end of the device.
High power semiconductor devices such as a diode, a bipolar transistor, a power MOSFET, an IGBT (Insulated Gate Bipolar Transistor), etc. employ the following technique to enhance their breakdown voltages. At a junction end of each device, a semi-insulating polycrystalline silicon film as a passivation film is in direct contact with the substrate of the device. Further, a diffusion layer of a low impurity concentration, i.e. a RESURF (Reduced Surface Field) layer, which has a conductivity opposite to that of the substrate, is formed in that surface portion of the substrate which is located just below the semi-insulating polycrystalline silicon film. This structure can reduce a surface electric field at the junction end. Accordingly, when switching off the power device, a depletion layer caused by a reverse voltage applied thereto uniformly expands. This results in an increase in breakdown voltage and also results in establishment of a stable operation.
The RESURF layer is formed in that surface portion of an N-type substrate, which is located between a P-type layer near a main junction area formed in the substrate, and an N+-channel stopper layer of a high impurity concentration formed in an end surface portion of the device. The RESURF layer is a P
−
-type layer of a low impurity concentration, and has one end thereof connected to the P-type layer and the other end thereof separated from the N
+
-channel stopper layer by a predetermined distance. The semi-insulating polycrystalline silicon film is formed on the RESURF layer.
Before forming the semi-insulating polycrystalline silicon film, an oxide film is formed on the entire substrate surface including the surface of the RESURF layer. When forming the semi-insulating polycrystalline silicon film, the oxide film is selectively removed by the photolithography technique, thereby forming an area for providing therein the semi-insulating polycrystalline silicon film. After that, the semi-insulating polycrystalline silicon film is formed on the entire substrate surface including the surface of the RESURF layer.
FIG. 5A
shows the concentration distribution of an impurity (boron) in the vicinity of the surface of the RESURF layer, obtained after the formation of the oxide film.
FIG. 5B
is an enlarged view of a portion indicated by (b) in
FIG. 5A
, showing the distribution of impurity concentration from the surface of the RESURF layer.
The concentration of the impurity in the RESURF layer surface reduces when, for example, boron diffuses into the oxide film while the oxide film grows. As is understood from
FIG. 5B
, the concentration especially reduces in a range of from the surface to a depth of 0.05 &mgr;m. This is not a desirable impurity concentration in the RESURF layer surface, and it is possible that the impurity concentration will be less than an allowable value.
In such a power semiconductor device, which has a RESURF surface of a low impurity concentration, breakdown voltage drift will easily occur. The breakdown voltage drift is a phenomenon in which a breakdown voltage against a reverse voltage will reduce over time. Accordingly, designed breakdown voltage characteristics will not be able to be obtained over time, which means that the life of the device is short.
BRIEF SUMMARY OF THE INVENTION
The present invention has been developed to solve the above problem, and aims to provide a highly reliable high-power semiconductor device capable of preventing its breakdown voltage from reducing due to breakdown voltage drift, and also to provide a method for manufacturing the device.
This aim is attained by the following device.
The high power semiconductor device of the invention has a RESURF layer at a junction end thereof. The surface of the substrate, which includes the RESURF layer, has a recess, in which a semiconductive film is formed. The depth of the recess reaches that portion of the RESURF layer which has a high impurity concentration. Accordingly, the surface of the RESURF layer does not have a portion of a low impurity concentration. This can prevent reduction of the breakdown voltage of the device, which means that the device can have a long life.
The aim of the invention is also attained by the following method.
In the high power semiconductor device of the invention, a RESURF layer is formed at a junction end thereof. The surface of the substrate, which includes the RESURF layer, is etched to form a recess. A semiconductive film is formed in the recess. The depth of the recess reaches that portion of the RESURF layer which has a high impurity concentration.
Accordingly, the surface of the RESURF layer does not have a portion of a low impurity concentration. This can prevent reduction of the breakdown voltage of the device, which means that the device can have a long life.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
REFERENCES:
patent: 5086332 (1992-02-01), Nakagawa et al.
patent: 5223919 (1993-06-01), Whight et al.
patent: 6054748 (2000-04-01), Tsukuda et al.
patent: 6069396 (2000-05-01), Funaki
patent: 6221760 (2001-04-01), Hamada
patent: 5-63213 (1993-03-01), None
patent: 08306937 (1996-11-01), None
Satou Shingo
Tsuchitani Masanobu
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Lee Eddie
Lee Eugene
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