Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With dam or vent for encapsulant
Reexamination Certificate
2002-01-17
2004-10-12
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With dam or vent for encapsulant
C257S788000, C257S787000, C257S778000
Reexamination Certificate
active
06803646
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a plurality of semiconductor elements stacked to each other and a method of fabricating the semiconductor device, and particularly to a technique capable of stacking semiconductor elements to each other without any limitation by outer sizes of the semiconductor elements.
If one semiconductor element is mounted on a wiring board, then an area of the wiring board is occupied with the semiconductor device, and thereby another semiconductor element is no longer mounted on the wiring board. On the other hand, in recent years, electronic devices such as video cameras, CDs, and cellular phones have been required to be further reduced in size and further enhanced in performance. To meet such a requirement, there has been proposed a semiconductor device, in which a semiconductor element mounting area becomes twice that of a prior art semiconductor device although the semiconductor device uses the same wiring board as that used for the related art semiconductor device.
For example, a related art semiconductor device
1
shown in
FIG. 4
includes two semiconductor elements
3
and
5
, wherein a surface (back surface)
9
opposed to an electric connection surface
7
of the semiconductor element
3
is superimposed to a surface (back surface)
13
opposed to an electric connection surface
11
of the other semiconductor element
5
and is bonded thereto by means of adhesive
15
, and the electric connection surface
11
of the upper semiconductor element
5
is electrically connected to segments of wiring on a wiring board
19
by means of bonding wires
17
while the electric connection surface
7
of the lower semiconductor element
3
is electrically connected to segments of the wiring on the wiring board
19
by means of bumps
23
.
Another related art semiconductor device
25
shown in
FIG. 5
includes two semiconductor elements
27
and
29
, in which a surface (back surface)
33
opposed to an electric connection surface
31
of the semiconductor element
27
is die-bonded to a wiring board
19
by means of adhesive
15
and electrodes of the semiconductor element
27
are electrically connected to segments of wiring on the wiring board
19
by means of bonding wires
17
, and the other semiconductor element
29
is bonded, in a flip-chip bonding manner, to a front surface of the semiconductor element
27
by means of bumps
35
.
With each of the semiconductor devices
1
and
25
, a mounting density of the semiconductor device becomes twice that of a conventional semiconductor device in which a mounting area is occupied with one semiconductor element. Accordingly, it is possible to miniaturize an electronic device using the semiconductor device.
The related art semiconductor device
1
shown in
FIG. 4
, however, has an inconvenience that an outer size of the lower layer semiconductor element must be larger than an electrode area, in which electrodes are disposed, of the upper layer semiconductor element. The reason for this is as follows: namely, at the time of connecting the bonding wires to respective electrodes of the upper layer semiconductor element, some support is required to be disposed directly under each of the electrodes of the upper layer semiconductor element. If such a support is not provided (that is, in an overhang state), when the bonding wire is connected to each electrode of the upper layer semiconductor element, a mechanical load is partially applied to the upper layer semiconductor element, resulting in breakage of the upper layer semiconductor element.
The related art semiconductor device
25
shown in
FIG. 5
has also an inconvenience that since the bonding wires must be connected to the lower layer semiconductor element, an outer size of the upper layer semiconductor element is required to be smaller than an electrode area, in which the electrodes are disposed, of the lower layer semiconductor element.
Accordingly, in each of the above-described related art semiconductor devices, there is a limitation to a relationship between the outer sizes of the lower layer semiconductor element and the upper layer semiconductor element. As a result, depending on a combination of outer sizes of semiconductor elements, the semiconductor devices cannot be stacked to each other, thereby failing to realize high density mounting of the semiconductor elements.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device capable of mounting semiconductor elements of arbitrary outer sizes to each other without any limitation by the outer sizes of the semiconductor elements, thereby realizing, even in a combination of any outer shapes of semiconductor elements vertically stacked to each other, high density mounting of the semiconductor elements, and to provide a method of fabricating the semiconductor device.
To achieve the above object, according to a first aspect of the present invention, there is provided a semiconductor device including: a first semiconductor element to be bonded to a wiring board in a flip-chip bonding manner; a resin peripheral wall formed on the wiring board in such a manner as to surround the first semiconductor element; a sealing resin poured so as to fill a space surrounded by the resin peripheral wall and then hardened; and a second semiconductor element provided in such a manner that a back surface thereof is fixed on an upper surface of the sealing resin and an electrode provided on a front surface thereof is connected to a segment of wiring on the wiring board by means of a bonding wire.
With this configuration, even if an outer size of the second semiconductor element is larger than that of the first semiconductor element, the second semiconductor element can be placed on the sealing resin. Accordingly, in the bonding step, a mechanical load applied to the second semiconductor element is supported by the sealing resin, so that it is possible to prevent occurrence of breakage of the second semiconductor element. As a result, the second semiconductor element of an arbitrary outer size can be stacked on the first semiconductor element without any limitation by the outer size of the first semiconductor element. That is to say, even in a combination of any outer shapes of semiconductor elements vertically stacked to each other, the semiconductor elements can be mounted at a high density.
In this semiconductor device, preferably, a portion, in the thickness direction, of the second semiconductor element is buried in the sealing resin, and the back surface of the second semiconductor element is supported on the back surface of the first semiconductor element via the sealing resin, and the front surface of the second semiconductor element is projected from the upper surface of the sealing resin.
With this configuration, since a portion, in the thickness direction, of the second semiconductor element is buried in the sealing resin, an adhesive strength of the second semiconductor element to the sealing resin can be improved. Also since the back surface of the second semiconductor element is supported on the back surface of the first semiconductor element via the sealing resin, it is possible to prevent the second semiconductor element from being excessively buried in the sealing resin and hence to realize accurate positioning of the second semiconductor element in the height direction. Further since the front surface of the second semiconductor element projects from the front surface of the sealing resin, it is possible to prevent electrodes provided on the front surface of the second semiconductor element from being covered with the sealing resin.
According to a second aspect of the present invention, there is provided a method of fabricating a semiconductor device, including the steps of: bonding a first semiconductor element on a wiring board in a flip-chip bonding manner; forming a resin peripheral wall on the wiring board in such a manner that the first semiconductor element is surrounded by the resin peripheral wall;
Smith Brad
Sonnenschein Nath & Rosenthal LLP
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