Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-05-31
2003-06-24
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S059000, C257S072000
Reexamination Certificate
active
06583471
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device having circuits formed by thin-film transistors (hereinafter designated as TFT) and relates to a method of manufacturing the semiconductor device. For example, this invention relates to an electrooptical device typified by a liquid crystal display panel and relates to electronic equipment provided with such electrooptical devices as components.
It should be first noted that a semiconductor device described in this specification signifies a general device workable by the use of semiconductor characteristics. In this sense, electrooptical devices, semiconductor circuits. and electronic equipment are all semiconductor devices.
2. Description of the Related Art
Development has advanced in a semiconductor device having large-area integrated circuits that are formed by TFTs on a substrate having an insulating surface. An active matrix type liquid crystal display, an EL display, and a close contact type image sensor are known as typical examples thereof. Specifically, a TFT in which a crystalline silicon film (typically, polysilicon film) is made an active layer (hereinafter, designated as polysilicon TFT) has greater electron field-effect mobility, and therefore, a variety of functional circuits can also be formed.
For example, the active matrix type liquid crystal display includes a pixel circuit for displaying an image for each functional block, a shift register circuit based on a CMOS circuit, a level shifter circuit, a buffer circuit, a driving circuit for controlling the pixel circuit, such as a sampling circuit. These circuits are formed on a single substrate.
The pixel circuit of the active matrix type liquid crystal display has hundreds of thousands to millions of pixels each of which is provided with a TFT, and the TFT has pixel electrodes. An opposite electrode is mounted on the opposite substrate side with a liquid crystal therebetween, thereby forming a kind of capacitor in which the liquid crystals serve as dielectrics. Furthermore, voltage applied to each pixel is controlled by the switching function of the TFT so as to control an electric charge to the capacitor, thereby driving the liquid crystals and controlling the amount of transmitted light. As a result, an image is displayed.
If the pixel circuit and the driving circuit are formed on the insulating surface, capacity (i.e., parasitic capacitance) is inevitably generated between multi-layer wirings to be formed.
The amount of the parasitic capacitance depends on an electrode area where a lower layer wiring and an upper layer wiring overlap, the film thickness of an insulating film between the overlapping lower and upper layer wirings, or other factors.
In recent years, as the reduction in the size and in the power consumption of a circuit advances, the influence of the parasitic capacitance has become too strong to ignore. For this reason, a proposal has been made to enlarge the electrode area of an auxiliary capacity in order to reduce the influence of the parasitic capacitance. However, a problem resides in that the aperture ratio of a pixel region is lessened if the electrode area is enlarged.
Additionally, if the lower layer wiring and the upper layer wiring are constructed not to overlap with each other, then the aperture ratio thereof is lessened similarly.
Especially, in the active matrix type liquid crystal display not more than an inch diagonally in size, the aperture ratio has received the greatest attention.
In order to improve the aperture ratio of the pixel region, attempts are being made. For example, the width of a wiring is narrowed not to enlarge a wiring area, or lower and upper layer wirings are laid on each other to the utmost limit so as to form multi-layer wirings.
In addition, a contact hole that reaches a source region and a drain region also has a reduced minute size by making circuits compact. A way of obtaining good contact connection is to taper the contact hole so as to form a lean. However, the size of the contact hole is increased by tapering it extremely. In a situation in which a microscopic contact hole whose diameter is about 0.5-1.5 &mgr;m, for example, is formed, etching defects, such as over-etching or etching residue, have occurred according to some etching conditions when an interlayer insulating film is thick, because the film thickness of a TFT in a source region or drain region is only 10 nm-50 nm.
The present invention is a technique for solving the aforementioned problems. Furthermore, it is an object of the present invention to reduce parasitic capacitance formed between multi-layer wirings and improve display characteristics in a semiconductor device, and additionally, to provide a manufacturing method for realizing such a semiconductor device.
SUMMARY OF THE INVENTION
A semiconductor device according to an aspect of the present invention disclosed in this specification is characterized in that it comprises a first wiring on an insulating surface, a first interlayer insulating film covering the first wiring, a second interlayer insulating film in contact with a part of the first interlayer insulating film, and a second wiring on the first and second interlayer insulating films, wherein the first and second interlayer insulating films are laminated together in a region where the first and second wirings overlap with each other.
In the aforementioned structure, an etching rate of the first interlayer insulating film is lower than that of the second interlayer insulating film.
Preferably, in the aforementioned structure, a selective ratio of an etching rate of the first interlayer insulating film to the second interlayer insulating film is 1.5 or more.
Additionally, in the aforementioned'structure, a film thickness of the first interlayer insulating film is 50-300 nm.
Additionally, in the aforementioned structure, a film thickness of the second interlayer insulating film is 150 nm-1 &mgr;m.
A semiconductor device according to another aspect of the invention including at least a TFT on an insulating surface is characterized in that a first interlayer insulating film, a second interlayer insulating film, and a second wiring are formed above a first wiring forming the TFF, and above a source region and drain region of the TFT, a gate insulating film, a first interlayer insulating film, and a second wiring are formed.
In the aforementioned structure, the sum of a film thickness of the gate insulating film and a film thickness of the first interlayer insulating film is 0.1 &mgr;m or more.
A semiconductor device according to still another aspect of the invention including at least a TFT on an insulating surface is characterized in that, above a first wiring forming the TFT, a second wiring exists via a first interlayer insulating film and second interlayer insulating film.
In the aforementioned structure, the TFT has a source region and a drain region, and the first interlayer insulating film is disposed over the source region or the drain region.
Additionally, in the aforementioned structure, the TFT is a reverse-stagger type TFT.
Additionally, in the aforementioned structure, the first wiring is a gate wiring.
A semiconductor device according to still another aspect of the present invention is characterized in that a semiconductor device including at least a pixel circuit and a driving circuit for controlling the pixel circuit, the circuit and the driving circuit disposed on a same substrate, comprises a pixel TFT forming the pixel circuit, the pixel TFT having a channel formation region, a gate insulating film, a gate wiring, a second wiring, and a plurality of insulating films, each having an etching rate different each other, wherein the channel formation region of the pixel TFT is formed to overlap with a part of the gate wiring with the gate insulating film therebetween, and the part of the gate wiring overlaps with the a second wiring with the plurality of insulating films therebetween.
In the aforementioned structure, the second wiring is a source line or a dra
Suzawa Hideomi
Yamagata Hirokazu
Yamazaki Shunpei
Cook Alex McFarron Manzo Cummings & Mehler, Ltd.
Ngo Ngan V.
Semiconductor Energy Laboratory Co,. Ltd.
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