Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – With inversion-preventing shield electrode
Patent
1995-05-31
1997-06-24
Prenty, Mark V.
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
With inversion-preventing shield electrode
257315, 257316, 257409, 257508, H01L 2358
Patent
active
056419899
ABSTRACT:
A semiconductor device includes a semiconductor substrate of a first conductivity type, a plurality of spaced field-shield isolation structures formed on a surface of the substrate and extending parallelly in a first direction to provide element-forming regions at spaces between every adjacent two of the field-shield element isolation layers, a pair of impurity diffusion layers of a second conductivity type different from the first conductivity type formed in the surface of the substrate at portions adjacent opposite sides of each of the element-forming regions, a plurality of spaced lateral regions defined on the surface of the substrate and extending parallelly in a second direction intersecting with the first direction; and a plurality of discrete gate electrodes formed on the surface of the substrate at portions corresponding to intersections of the lateral and element-forming regions, respectively, in electrically insulated relationship with the substrate, the gate electrodes being aligned along the lateral regions. The semiconductor elements are formed at the intersections, respectively, each semiconductor element having a pair of portions of the impurity diffusion layers disposed at one of the intersection, and a channel region is formed between the portions of the diffusion layers and one of the gate electrodes formed at the one intersection. Also a method of making the semiconductor device includes respective steps of forming the above components constituting the semiconductor device.
REFERENCES:
patent: 5164806 (1992-11-01), Nagatomo et al.
patent: 5498898 (1996-03-01), Kawamura
1988 IEDM, pp. 246-249, by Wakamiya et al., Dec. 1988.
A 3.6 um.sup.2 Memory Cell Structure for 16 MB EPROM, Y. Hisamune et al., IEDM-89, Dec. 1989, pp. 583-586.
Nippon Steel Corporation
Prenty Mark V.
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