Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-03-09
2003-08-05
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S308000, C257S311000
Reexamination Certificate
active
06603161
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-066734, filed Mar. 10, 2000; No. 2000-087403, filed Mar. 27, 2000; and No. 2000-087417, filed Mar. 27, 2000, the entire contents of all of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a ferroelectric capacitor and a method for manufacturing the ferroelectric capacitor.
Ferroelectric substances have a hysteresis characteristic between applied electric fields and the amount of electric polarization; thus, polarization remains even if a voltage applied between opposite ends of the ferroelectric substance is returned to zero. That is, the ferroelectric substance is characterized in that electric polarization generated when electric fields are applied remains even after the application of electric fields has been stopped and in that the direction of the polarization is reversed when electric fields of a certain intensity or more are applied in a direction opposite to that of the above electric fields.
Memory which consists of series connected memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor inbetween the two terminals, hereafter named “Series connected TC unit type ferroelectric RAM” is gathering the industry's attention. In these Series connected TC unit type ferroelectric RAMs, the cell area per memory cell is reduced based on the non-volatile characteristic of ferroelectric substances, by connecting opposite ends of a ferroelectric capacitor (C) between a source and a drain of a cell transistor (T) to constitute a unit cell and connecting a plurality of such unit cells in series.
These Series connected TC unit type ferroelectric RAMs are known, for example, from “High-Density Chain Ferroelectric Random Access Memory (CFRAM)”, VLSI Circuit Symposium, 1997, p. 83-84, “A Sub-40 ns Random-Access Chain FRAM Architecture with 7 ns Cell-Plate-Line Drive”, ISSCC Tech. Digest Papers, pp. 102-103, February 1999, and “Ferro Electric RAM”, D. Takashima et al., JSSCC, pp. 787-792, May 1998”.
FIG. 1
shows an equivalent circuit of the Series connected TC unit type ferroelectric RAMs described in these documents. In this figure, eight transistors T
0
to T
7
are connected in series, and ferroelectric capacitors are each connected between a source and a drain of a corresponding one of the transistors to constitute a cell array block. The cell array block has one end connected to a bit line BL via a selection gate transistor ST
1
and the other end connected to a plate line PL via a selection gate transistor ST
2
(or directly).
The transistors T
0
to T
7
have their gates connected to word lines WL
0
to WL
7
, respectively, and the selection gate transistors ST
1
and ST
2
have their gates connected to selection gate lines BS
1
and BS
2
, respectively. Specifically, the word lines WL
0
to WL
7
and the selection gate lines BS
1
and BS
2
are configured by continuously forming corresponding gate electrodes between a plurality of other cell array blocks (not shown).
The Series connected TC unit type ferroelectric RAMs are advantageous in that the unit cell area can be reduced by sharing a diffusion layer of the adjacent transistor within the cell array block; theoretically, these memories can achieve 4F
2
(F denotes a minimum size). Further, the area occupied by peripheral circuits can be reduced compared to ordinary ferroelectric memories, thereby reducing the chip size and costs.
The Series connected TC unit type ferroelectric RAMs also have an excellent characteristic that the plate line PL connected to the other end can be formed of the diffusion layer formed outside the cell array and thus has low resistance, whereby drivers are not required to have high performance. The Series connected TC unit type ferroelectric RAMs can thus operate faster than ordinary ferroelectric memories.
As described above, the Series connected TC unit type ferroelectric RAMs have various characteristics, but also have problems.
That is, for memory cells of a capacitor on plug (COP) structure in which, for example, a tungsten plug (W plug) is formed on a source and a drain diffusion layer of a transistor as a contact plug with a ferroelectric capacitor formed on the W plug, a barrier metal must be interposed between the W plug and the ferroelectric capacitor to prevent oxidation of the W plug, but no metal has been found suitable to be such a barrier metal.
Thus, an upper and a lower electrode of the ferroelectric capacitor are connected to the source and drain diffusion layers of the transistor by separately forming metal wiring.
FIGS. 2A
to
2
E show a conventional method for manufacturing a ferroelectric capacitor for a series connected TC unit type ferroelectric RAM, in the order of steps.
First, as shown in
FIG. 2A
, a lower electrode
12
, a ferroelectric film
13
, and an upper electrode
14
are sequentially deposited on an interlayer insulating film
11
provided on a semiconductor substrate.
Then, as shown in
FIG. 2B
, an etching mask
15
having a predetermined pattern shape is formed and used to etch the upper electrode
14
.
Then, the mask
15
is removed and a new etching mask
16
having a predetermined pattern shape is subsequently formed as shown in FIG.
2
C. In this case, the mask
16
is shaped so as to continuously cover the two upper electrodes
14
. The mask
16
us used to etch the remaining part of the ferroelectric film
13
and lower electrode
12
.
Then, as shown in
FIG. 2D
, an interlayer insulating film
17
is deposited on the entire top surface, wiring grooves
18
and contact holes
19
for the two upper electrodes
14
are formed in the interlayer insulating film
17
, and a wiring groove
20
and a contact hole
21
for the lower electrode
12
are further formed.
Subsequently, contact plugs/wires
22
are formed so as to fill the wiring grooves
18
and
20
and the contact holes
19
and
21
. The contact plugs/wires
22
are connected to a source and a drain diffusion layers of a transistor (not shown).
In this conventional method, when the contact hole
21
for the lower electrode
12
is formed, the interlayer insulated layer
17
and the ferroelectric film
13
must be etched. An etching rate for the ferroelectric film is low, about one tenth (for example, 50 nm/sec.) of that for the interlayer insulating film, thus requiring a large amount of time to form the deep contact hole
21
for the lower electrode
12
. Consequently, when the contact holes
19
for the upper electrodes
14
are formed, relatively large parts of the upper electrodes
14
are removed as shown in
FIG. 2D
, thereby disadvantageously degrading capacitor characteristics or inducing capacitor leakage.
Furthermore, it has been found that since the contact hole
21
for the lower electrode
12
penetrates the ferroelectric film
13
, an etching gas may damage the ferroelectric film to degrade polarization.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made in view of the foregoing. An object of the invention is to provide a semiconductor device, a semiconductor storage device and a method of manufacturing the same, in which the degradation of capacitor characteristics or the capacitor leakage is prevented when a part of the upper electrode is etched in the process of making contact holes and in which the damage to the ferroelectric film is reduced to prevent the deterioration of the ferroelectric capacitor, which would otherwise occur due to polarization.
According to the present invention, there is provided a semiconductor device comprising a first interlayer insulating film formed on a semiconductor substrate, a lower electrode formed on the first interlayer insulating film, a pair of ferroelectric films formed on the lower electrode separately from each other, and a pair of upper electrode formed on the pair of ferroelectric films, wherein the lower electrode, the
Kanaya Hiroyuki
Kumura Yoshinori
Ozaki Tohru
Taniguchi Yasuyuki
Eckert George
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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